DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (U.S. Patent Application Publication No. 2019/0096851).
Regarding to claim 1, Liao teaches a method of manufacturing a semiconductor device, the method comprising:
encapsulating a first electrical structure and a second electrical structure in a first encapsulant (Fig. 1A, element 19), the first electrical structure having a first set of external electrical connections (Fig. 1A, element 16 on left die), the second electrical structure having a second set of external electrical connections (Fig. 1A, element 16 on right die);
after encapsulating the first electrical structure and the second electrical structure, electrically coupling a bridge component to a first subset of the first set of external electrical connections and to a first subset of the second set of external electrical connections, the bridge component overlapping the first electrical structure and the second electrical structure (Fig. 1G, element 27);
forming through insulator vias on a second subset of the first set of electrical connections and on a second subset of the second set of electrical connections (Fig. 1G, element 24);
after forming the through insulator vias, encapsulating the bridge component and the through insulator vias with a second encapsulant (Fig. 1H, element 30); and
forming a redistribution structure over the second encapsulant and the through insulator vias (Fig. 1J, element 32 (RDL1-4)).
Regarding to claim 4, Liao teaches conductive features of the bridge component are directly bonded to the first subset of the first set of external electrical connections (Fig. 1G).
Regarding to claim 5, Liao teaches conductive features of the bridge component are electrically coupled to the first subset of the first set of external electrical connections using solder joints (Fig. 1G, element 28).
Regarding to claim 7, Liao teaches the bridge component is between two of the through insulator vias (Fig. 1G).
Claims 1-3, 5, 7-8, 11-12, 14, 16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (U.S. Patent No. 9,735,131).
Regarding to claim 1, Su teaches a method of manufacturing a semiconductor device (Fig. 4, Fig. 16), the method comprising:
encapsulating a first electrical structure and a second electrical structure in a first encapsulant (Fig. 4, Fig. 16, element 48), the first electrical structure having a first set of external electrical connections (Fig. 4, Fig. 16, element 44 on left die), the second electrical structure having a second set of external electrical connections (Fig. 4, Fig. 16, element 44 on right die);
after encapsulating the first electrical structure and the second electrical structure, electrically coupling a bridge component to a first subset of the first set of external electrical connections and to a first subset of the second set of external electrical connections, the bridge component overlapping the first electrical structure and the second electrical structure (Fig. 6, Fig. 16, element 58);
forming through insulator vias on a second subset of the first set of electrical connections and on a second subset of the second set of electrical connections (Fig. 6, Fig. 16, element 56);
after forming the through insulator vias, encapsulating the bridge component and the through insulator vias with a second encapsulant (Fig. 8, element 66); and
forming a redistribution structure over the second encapsulant and the through insulator vias (Fig. 8, Fig. 16, element 70).
Regarding to claim 2, Su teaches the first electrical structure comprises a first die attached to a first interposer, the first die being encapsulated by a third encapsulant, a surface of the third encapsulant and a surface of the first encapsulant being level (Fig. 16, element 34’).
Regarding to claim 3, Su teaches the first die is attached to the first interposer using solder joints (Fig. 16, element 536).
Regarding to claim 5, Su teaches conductive features of the bridge component are electrically coupled to the first subset of the first set of external electrical connections using solder joints (Fig. 16, element 62).
Regarding to claim 7, Su teaches the bridge component is between two of the through insulator vias (Fig. 8, Fig. 16).
Regarding to claim 8, Su teaches a method of manufacturing a semiconductor device, the method comprising:
bonding a first semiconductor device to a first interposer (Fig. 16, please see annotations in the attached figure);
encapsulating the first semiconductor device with a first encapsulant to form a first structure (Fig. 16, please see annotations in the attached figure);
bonding a second semiconductor device to a second interposer different from the first interposer (Fig. 16, please see annotations in the attached figure);
encapsulating the second semiconductor device with a second encapsulant, wherein the second encapsulant is different than the first encapsulant to form a second structure (Fig. 16, please see annotations in the attached figure);
after encapsulating the first semiconductor device and encapsulating the second semiconductor device, encapsulating the first structure and the second structure with a third encapsulant (Fig. 16, please see annotations in the attached figure);
connecting a bridge component to the first interposer and the second interposer, the bridge component electrically coupling the first interposer to the second interposer (Fig. 16, please see annotations in the attached figure); and
electrically connecting a substrate to the first interposer and the second interposer (Fig. 16, please see annotations in the attached figure, the substrate is electrically connecting to the first and second interposers via connections in the bridge die),
wherein the bridge component is between the substrate and the first interposer and between the substrate and the second interposer (Fig. 16, please see annotations in the attached figure).
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Regarding to claim 11, Su teaches forming through insulator vias on the first interposer and the second interposer, wherein electrically connecting the substrate comprises electrically connecting the substrate to the through insulator vias (Fig. 16, element 58).
Regarding to claim 12, Su teaches the substrate completely covers the bridge component (Fig. 16).
Regarding to claim 14, Su teaches connecting the bridge component to the first interposer and the second interposer comprises performing a reflow process (column 5, lines 55-56).
Regarding to claim 16, Su teaches a method of manufacturing a semiconductor device, the method comprising:
bonding a first substrate to a semiconductor structure (Fig. 16), wherein the semiconductor structure comprises:
a bridge component (Fig. 16, please see annotations in the attached figure);
a first interposer electrically connected to the bridge component (Fig. 16, please see annotations in the attached figure);
a second interposer electrically connected to the bridge component, wherein the bridge component electrically couples the first interposer to the second interposer (Fig. 16, please see annotations in the attached figure);
a first semiconductor device bonded to the first interposer and surrounded by a first encapsulant (Fig. 16, please see annotations in the attached figure); and
a second semiconductor device bonded to the second interposer and surrounded by a second encapsulant (Fig. 16, please see annotations in the attached figure).
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Regarding to claim 18, Su teaches the semiconductor structure further comprises a third encapsulant surrounding the first encapsulant and the second encapsulant.
Regarding to claim 19, Su teaches the semiconductor structure further comprises a third encapsulant surrounding the first encapsulant and the second encapsulant (Fig. 16, element 58).
Regarding to claim 20, Su teaches a third encapsulant along sidewalls of the bridge component and the through vias (Fig. 16, element 66).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. Patent No. 9,735,131), as applied to claim 1 above, in view of Mallik et al. (U.S. Patent Application Publication No. 2021/0005542).
Regarding to claim 6, Su does not explicitly disclose the bridge component comprises through vias. Mallik discloses a bridge component comprises through vias (Fig. 1A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Su in view of Mallik to comprise through vias in the bridge component in order to make the structure useful for a particular application.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. Patent No. 9,735,131), as applied to claim 8 above, in view of Elsherbini et al. (U.S. Patent No. 11,494,682).
Regarding to claim 13, Su does not explicitly disclose connecting the bridge component to the first interposer and the second interposer comprises hybrid bonding the bridge component to the first interposer and the second interposer. Elsherbini discloses connecting bridge component to first component and second component comprises hybrid bonding the bridge component to the first component and the second component (Fig. 1, column 11, lines 20-24). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Su in view of Elsherbini to hybrid bond the bridge component to the first interposer and the second interposer in order to increase adhesion.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. Patent No. 9,735,131), as applied to claim 16 above, in view of Elsherbini et al. (U.S. Patent No. 11,494,682).
Regarding to claim 17, Su does not explicitly disclose the bridge component is hybrid bonded to the first interposer and the second interposer. Elsherbini discloses the bridge component is hybrid bonded to the first component and the second component (Fig. 1, column 11, lines 20-24). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Su in view of Elsherbini to hybrid bond the bridge component to the first interposer and the second interposer in order to increase adhesion.
Allowable Subject Matter
Claims 9-10 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the first semiconductor device comprises a semiconductor die attached to an interface structure, the semiconductor die being encapsulated with a fourth encapsulant” in combination with the limitations recited in claim 8.
Regarding to claim 15, the prior art fails to anticipate or render obvious the claimed limitations including “bonding a third semiconductor device to the first interposer, wherein the first semiconductor device is a logic device and the third semiconductor device is a high bandwidth memory” in combination with the limitations recited in claim 8.
Pertinent Art
For the benefits of the Applicant, US-11164817-B2, US-11462480-B2, US-20210005542-A1, US-10262974-B2, US-10522470-B1, US-9997446-B2, US-20150364422-A1, US-10833052-B2, and US-20200075561-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose electrically connecting a substrate to the first interposer and the second interposer, wherein the bridge component is between the substrate and the first interposer and between the substrate and the second interposer.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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