DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-3 and 5-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12142685 (hereinafter CHIANG) in view of ZHU (US 20090008705).
Regarding claim 1, CHIANG discloses a fin structure extending from a base substrate layer (see claim 1), wherein the fin structure includes a first fin portion having a first width (see claim 1), a second fin portion having a second width disposed over the first fin portion (see claim 1), and a third fin portion having a third width disposed over the second fin portion (see claim 1), wherein:
the first fin portion is a protrusion of the base substrate layer (see claim 1),
the second width is greater than the first width and the third width (see claim 1), and
a first composition of the first fin portion is different than a second composition of the second fin portion (see claim 1);
an isolation feature over the base substrate layer, wherein the isolation feature abuts first sidewalls of the first fin portion, second sidewalls of the second fin portion, a top surface of the second fin portion, and third sidewalls of the third fin portion (see claim 1); and
wherein the top surface of the second fin portion extends along a fin widthwise direction between the second sidewalls of the second fin portion, the third fin portion is disposed on the top surface of the second fin portion, and the top surface of the second fin portion extends a distance along the fin widthwise direction beyond the third sidewalls of the third fin portion (see claim 1).
CHIANG fails to explicitly disclose a method comprising:
forming a fin structure;
forming an isolation feature.
ZHU discloses a method (the method shown in fig 1-9, see para 45) comprising:
forming a fin structure (the fin formed in fig 2, see para 54);
forming an isolation feature (the oxide isolation feature 62 is formed, see fig 4A, para 56).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
Regarding claim 2, CHIANG and ZHU disclose the method of claim 1.
CHIANG further discloses, wherein the forming of the fin structure provides the first width substantially uniform from a top to a bottom of the first fin portion and the third width substantially uniform from a top to a bottom of the third fin portion (see claim 2).
Regarding claim 3, CHIANG and ZHU disclose the method of claim 1.
CHIANG further discloses, wherein the isolation feature is formed to abut a bottom portion of the third sidewalls of the third fin portion, and the isolation feature is formed to not abut an upper portion of the third sidewalls of the third fin portion (see claim 3).
Regarding claim 5, CHIANG and ZHU disclose the method of claim 1.
CHIANG further discloses, wherein the third width is less than the first width (see claim 5).
Regarding claim 6, CHIANG and ZHU disclose the method of claim 1.
CHIANG fails to explicitly disclose, wherein the forming the fin structure includes:
forming a semiconductor layer over the base substrate layer;
patterning the semiconductor layer and the base substrate layer to form a semiconductor fin, wherein the semiconductor fin has the first width, and further wherein the semiconductor fin includes a semiconductor layer portion and a base substrate layer portion;
enlarging a lower portion of the semiconductor layer portion, such that the lower portion of the semiconductor layer portion has the second width; and
trimming an upper portion of the semiconductor layer portion, such that the upper portion of the semiconductor layer portion has the third width.
ZHU discloses, wherein the forming the fin structure includes:
forming a semiconductor layer over the base substrate layer (the semiconductor layer 32 and 40 is formed on top of the substrate 10, 20 and 30, see fig 1, para 49);
patterning the semiconductor layer and the base substrate layer to form a semiconductor fin (the fin comprising 30, 32 and 40 is patterned, see fig 2 para 54), wherein the semiconductor fin has the first width (40 has a first width, see fig 2C), and further wherein the semiconductor fin includes a semiconductor layer portion and a base substrate layer portion (the fin includes parts of 30, 32 and 40, see fig 2C);
enlarging a lower portion of the semiconductor layer portion, such that the lower portion of the semiconductor layer portion has the second width (32 can be enlarged by oxidation which forms 53, see fig 5, para 57); and
trimming an upper portion of the semiconductor layer portion, such that the upper portion of the semiconductor layer portion has the third width (removing 56 to reduce the width of 40, see fig 9, para 61).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
Regarding claim 7, CHIANG and ZHU disclose the method of claim 6.
CHIANG fails to explicitly disclose, wherein enlarging the lower portion of the semiconductor layer portion includes performing a thermal oxidation process.
ZHU discloses, wherein enlarging the lower portion of the semiconductor layer portion includes performing a thermal oxidation process (54 is formed as 53 by thermal oxidation, see fig 9, para 57).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
Regarding claim 8, CHIANG and ZHU disclose the method of claim 6.
CHIANG further discloses, wherein:
the semiconductor layer includes a first semiconductor material and a second semiconductor material, wherein the second semiconductor material is disposed over the first semiconductor material, and the base substrate layer includes a third semiconductor material (see claim 6); and
the lower portion of the semiconductor layer portion is the first semiconductor material, and the upper portion of the semiconductor layer portion is the second semiconductor material (see claim 6).
Regarding claim 9, CHIANG discloses a fin structure having a first fin portion having a first width extending from a substrate, a second fin portion having a second width disposed over the first fin portion, and a third fin portion having a third width disposed over the second fin portion (see claim 9);
a first dielectric layer that abuts first sidewalls of the first fin portion, second sidewalls of the second fin portion, and third sidewalls of the third fin portion (see claim 9), wherein:
the first sidewalls of the first fin portion are smooth along a first height thereof, the second sidewalls of the second fin portion are smooth along a second height thereof, and the third sidewalls of the third fin portion are smooth along a third height thereof (see claim 9), and
a sum of the first height, the second height, and the third height is a total height of the fin structure, wherein the second width along an entirety of the second height is greater than the first width along an entirety of the first height and the third width along an entirety of the third height (see claim 9); and
a second dielectric layer that abuts the first dielectric layer and the third sidewalls of the third fin portion, wherein a portion of the first dielectric layer extends from a bottom surface of the second dielectric layer to a top surface of the second fin portion and the portion of the first dielectric layer abuts the bottom surface of the second dielectric layer and the top surface of the second fin portion (see claim 9).
CHIANG fails to explicitly disclose a method comprising:
forming a fin structure;
forming a first dielectric layer;
forming a second dielectric layer.
ZHU discloses a method (the method shown in fig 1-9, see para 45) comprising:
forming a fin structure (the fin formed in fig 2, see para 54);
forming a first dielectric layer (62 is formed, see fig 4, para 56);
forming a first dielectric layer (62 is formed, see fig 4, para 56).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
Regarding claim 10, CHIANG and ZHU disclose the method of claim 9.
CHIANG further discloses, wherein the first dielectric layer is formed of a first dielectric material, the second dielectric layer is formed of a second dielectric material, and the first dielectric material is the same as the second dielectric material (see claim 10).
Regarding claim 11, CHIANG and ZHU disclose the method of claim 10.
CHIANG further discloses, wherein the first dielectric material includes silicon and oxygen, and the second dielectric material includes silicon and oxygen (see claim 11).
Regarding claim 12, CHIANG and ZHU disclose the method of claim 9.
CHIANG further discloses, wherein the first dielectric layer is formed of a first dielectric material, the second dielectric layer is formed of a second dielectric material, and the first dielectric material is different than the second dielectric material (see claim 13).
Regarding claim 13, CHIANG and ZHU disclose the method of claim 12.
CHIANG further discloses, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes oxygen (see claim 12).
Regarding claim 14, CHIANG and ZHU disclose the method of claim 9.
CHIANG further discloses, wherein the first dielectric layer is formed to wrap the second fin portion (see claim 14).
Regarding claim 15, CHIANG and ZHU disclose the method of claim 9.
CHIANG further discloses, wherein the first dielectric layer is a portion of an isolation feature, and the second dielectric layer is a portion of a gate structure (see claim 15).
Regarding claim 16, CHIANG discloses a first fin structure and a second fin structure over a substrate (see claim 16), wherein:
the first fin structure and the second fin structure each have an etched substrate fin portion having a first width, a first fin portion having a second width disposed directly on and above the etched substrate fin portion, and a second fin portion having a third width disposed directly on and above the first fin portion, wherein the second width is greater than the first width and the third width (see claim 16), and
the etched substrate fin portion has first linear sidewalls and the second fin portion has second linear sidewalls (see claim 16); and
an isolation feature over the substrate and between the first fin structure and the second fin structure, wherein the isolation feature is formed to cover an entirety of first sidewalls of the etched substrate fin portions of the first fin structure and the second fin structure, an entirety of second sidewalls of the first fin portions of the first fin structure and the second fin structure, and lower portions of third sidewalls of the second fin portions of the first fin structure and the second fin structure (see claim 16).
CHIANG fails to explicitly disclose A method comprising:
forming a first fin structure and a second fin structure;
forming an isolation feature.
ZHU discloses a method (the method shown in fig 1-9, see para 45) comprising:
forming a fin structure (the fin formed in fig 2, see para 54);
forming an isolation feature (the oxide isolation feature 62 is formed, see fig 4A, para 56).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
Regarding claim 17, CHIANG and ZHU disclose the method of claim 16.
CHIANG further discloses, wherein the etched substrate fin portions of the first fin structure and the second fin structure have substantially the same height (see claim 17).
Regarding claim 18, CHIANG and ZHU disclose the method of claim 16.
CHIANG further discloses, further comprising forming a gate structure that covers upper portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure, wherein the gate structure is disposed directly on the isolation feature (see claim 18).
Regarding claim 19, CHIANG and ZHU disclose the method of claim 16.
CHIANG further discloses, wherein:
the second fin portions of the first fin structure and the second fin structure have a first height in channel regions of the first fin structure and the second fin structure and a second height in source/drain regions of the first fin structure and the second fin structure (see claim 19); and
the isolation feature is formed to cover the lower portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure in the channel regions and cover the lower portions and the upper portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure in the source/drain regions (see claim 19).
Regarding claim 20, CHIANG and ZHU disclose the method of claim 16.
CHIANG further discloses, wherein the isolation feature is formed to abut laterally extending top surfaces of the first fin portions of the first fin structure and the second fin structure (see claim 20).
Claims 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12142685 (hereinafter CHIANG) in view of ZHU (US 20090008705) and further in view of RACHMADY (US 20140225065).
Regarding claim 4, CHIANG and ZHU disclose the method of claim 1.
CIANG further discloses a device, further comprising:
a dielectric layer that abuts a top surface of the third fin portion in a first region of the fin structure (see claim 4); and
an epitaxial layer that abuts the top surface of the third fin portion in second regions of the fin structure, wherein the first region of the fin structure is disposed between the second regions of the fin structure (see claim 4).
ZHU further discloses forming a dielectric layer (the dielectric 56 can be formed, see fig 5, para 57).
CHIANG and ZHU are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the claims of CHIANG with the method including forming layers of ZHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the claims of CHIANG with the method including forming layers of ZHU in order to avoid shortening the length of the channel (see ZHU para 68).
CHIANG and ZHU fail to explicitly disclose forming an epitaxial layer.
RACHMADY discloses forming an epitaxial layer (the epi source/drain layers 338 and 339, see fig 3E, para 41).
CHIANG, ZHU And RACHMADY are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHIANG and ZHU with the forming of the epi layer of RACHMADY because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHIANG and ZHU with the forming of the epi layer of RACHMADY in order to increase drive current (see RACHMADY para 21).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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