Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 7/26/24. Claims 1-20 are pending.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US PGPub 2020/0135851, hereinafter referred to as “Lin”).
Lin discloses the semiconductor method as claimed. See figures 1A-3D and 21, and corresponding text, where Lin teaches, in claim 1, a semiconductor arrangement, comprising:
a gate electrode (110), comprising:
a first portion over a first interface between an active region (106) and an isolation structure (104); and a second portion over the active region (106), wherein:
the first portion of the gate electrode (114) has a first material composition, and the second portion of the gate electrode (116) has a second material composition different than the first material composition (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 2, wherein: the first material composition has a first work function, and the second material composition has a second work function different than the first work function (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 3, wherein: the first material composition has a first work function type, and the second material composition has a second work function type opposite the first work function type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 4, wherein: the first material composition comprises a first metal, and the second material composition comprises a second metal different than the first metal (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 5, wherein: the first material composition comprises silicon, and the second material composition comprises a first metal having a first work function with a first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 5, wherein: the first material composition comprises an impurity having a second conductivity type opposite the first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 7, wherein: the first portion of the gate electrode comprises a silicide having a second work function with a second conductivity type opposite the first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 8, comprising: a dielectric layer between the first portion of the gate electrode and the second portion of the gate electrode (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 9, wherein: the first material composition comprises silicon and a first impurity having a first conductivity type, and the second material composition comprises silicon and a second impurity having a second conductivity type opposite the first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 10, comprising: a gate dielectric, wherein: a first portion of a sidewall of the first portion of the gate electrode is separated from a first portion of a sidewall of the second portion of the gate electrode by the gate dielectric, and a second portion of the sidewall of the first portion of the gate electrode is in contact with a second portion of the sidewall of the second portion of the gate electrode (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 11, comprising a cap layer extending over the first portion of the gate electrode and the second portion of the gate electrode (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 12, comprising a sidewall spacer overlying the isolation structure (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 13, wherein the isolation structure forms a closed-loop (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 14, a semiconductor arrangement, comprising:
a gate electrode (110), comprising:
a first portion over a first interface between an active region (106) and an isolation structure (104); and a second portion over the active region (106), wherein:
the active region comprises a first impurity having a first conductivity type, the first portion of the gate electrode has a first work function, the second portion of the gate electrode has a second work function different than the first work function, and the second work function has the first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 15, wherein the first work function has a second conductivity type opposite the first conductivity type (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 16, comprising: a sidewall spacer in contact with the isolation structure (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 17, comprising: a cap layer over the first portion of the gate electrode and the second portion of the gate electrode (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 19, a semiconductor arrangement, comprising:
a gate electrode (110); and
a gate dielectric layer, wherein the gate dielectric layer partially separates a first portion of the gate electrode from a second portion of the gate electrode in a vertical direction extending perpendicular to a top surface of the gate electrode (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 19, wherein a sidewall of the first portion of the gate electrode and a sidewall of the second portion of the gate electrode partially contact each other (figures 1A-1B; [0024-0027]).
Lin teaches, in claim 20, wherein the first portion of the gate electrode overlies an isolation structure (figures 1A-1B; [0024-0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANETTA D ISAAC/Examiner, Art Unit 2898 August 8, 2026
Prosecution Insights