3DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
PRIORITY CLAIM AND CROSS-REFERENCE
2. This patent is a continuation of U.S. Application No. 17/883,999, filed on August 9, 2022, entitled “Die On Die Bonding Structure,” now U.S. Patent No. 12,125,819, issued Oct 22, 2024, which is a divisional of U.S. Application No. 17/186,984, filed on February 26, 2021, now U.S. Patent No. 11,715,723, issued August 1, 2023, entitled “Wafer On Wafer Bonding Structure,” each application is hereby incorporated by reference herein as if reproduced in its entirety.
Double Patenting
3. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
4. Claims 1 and 7 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 12125819-B2 (here and after ‘819) in view of claims 1-20 of U.S. Patent No. US 9666502 B2 (here and after ‘502). Although the conflicting claims are not identical, they are not patentably distinct from each other because of the following rationale.
5. Claims 1 and 7 read in claims 1 and 5 of U.S. Patent No. 12,125,819-B2 respectively with no non-obvious difference between the subject matter included in pending 1 and 7, and in claims 1 and 5 of ‘819. The only difference as a comprising claim being “molding compound along sidewalls of the first device” as disclosed in claim 1 from the application. As both references disclose a package structure semiconductor device with similar structure, the differences between these claims and the claims of ‘819 in view of claims ‘502 are seen as obvious.
Therefore, at the time of invention, it would have been obvious to a person having ordinary skill in the art having the teachings of the instant application and the claims of ‘819 in view of claims ‘502 to modify the interconnect structure of ‘819 with the feature as taught by ‘502, because molding materials in semiconductor packages are essential for protecting the chip from physical and environmental damage, providing electrical insulation, ensuring mechanical stability, and enabling reliable, high‑density assembly.
As per claims 2-6, these claims are at least rejected for their dependencies, directly or indirectly, on the rejected claims 1 and 7 above. Therefore, they are rejected for the same reason set forth in paragraph above.
6. The following table shows the corresponding conflicting claims between the instant application and U.S. Patent No. 12,125,819-B2.
Application 18/785335
U.S. Patent No. 12,125,819-B2
1. A package comprising: a first device, wherein the first device comprises a first semiconductor substrate, a first interconnect on a first surface of the first semiconductor substrate, and metal vias extending through the first semiconductor substrate and protruding from a second surface of the first semiconductor substrate; molding compound along sidewalls of the first device; a first insulating bonding layer on the first surface of the first semiconductor substrate, wherein a surface of the metal vias is level with a surface of the first insulating bonding layer; and a second device bonded to the first device, wherein the second device comprises a second insulating bonding layer and bond pads in the second insulating bonding layer, wherein at a bonding interface between the first device and the second device the metal vias of the first device are directly bonded to the bond pads of the second device, wherein the first insulating bonding layer is fused to the second insulating bonding layer of the second device, the first insulating bonding layer disposed at a back side of the first device.
1. A package component comprising: a first device bonded to a second device, wherein the first device comprises a semiconductor substrate, a first insulating bonding layer on a first surface of the semiconductor substrate, a first interconnect on a second surface of the semiconductor substrate, and metal vias extending through the semiconductor substrate, the first insulating bonding layer, and the first interconnect, wherein the second device comprises a second insulating bonding layer and bond pads in the second insulating bonding layer, wherein at a bonding interface between the first device and the second device the metal vias of the first device are directly bonded to the bond pads of the second device and the first insulating bonding layer of the first device is fused to the second insulating bonding layer of the second device, the first insulating bonding layer disposed at a back side of the first device.
7. The package of claim 1, wherein the first insulating bonding layer is between 0.8 μm and 3 μm thick.
5. The package component of claim 1, wherein, a first dielectric material of the first insulating bonding layer is the same as a second dielectric material of the second insulating bonding layer; and wherein the first insulating bonding layer and the second insulating bonding layer are each between 0.8 μm and 3 μm thick.
Allowable Subject Matter
Claims 1-7 would be allowable over the prior art of record upon a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d).
5. Claims 8-20 are allowed.
Reasons for Allowance
6. The following is an examiner's statement of reasons for allowance:
7. Regarding claims 8-14, the prior art failed to disclose or reasonably suggest a first bonding layer on the second side of the first semiconductor substrate, wherein the first set of vias protrude through the first bonding layer; a second device structure, the second device structure comprising a second semiconductor substrate, a second set of vias, second active devices, a second interconnect structure on a first side of the second semiconductor substrate, a first front bonding layer on the second interconnect structure, bonding pads in the first front bonding layer, and a first reverse bonding layer on a second side of the second semiconductor substrate, the first reverse bonding layer comprising a first dielectric material, the first front bonding layer being bonded to the first bonding layer, wherein the bonding pads are directly bonded to the first set of vias, wherein the second set of vias traverse through the second semiconductor substrate and the first reverse bonding layer; and a third device structure, the third device structure comprising a third substrate, a third set of vias, third active devices, a third interconnect structure, and a second front bonding layer, wherein the third set of vias traverse from the second front bonding layer through the third device structure to a back side of the third device structure, wherein the third device structure is electrically connected to the second device structure.
8. Regarding claims 15-20, the prior art failed to disclose or reasonably suggest a first insulating bonding layer on the first surface of the first semiconductor substrate and a surface of the molding compound, wherein the first through via extends through the first insulating bonding layer; and a second device structure bonded to the first device structure, wherein the second device structure comprises a second insulating bonding layer and a bond pad in the second insulating bonding layer, wherein a surface of the bond pad is directly bonded to the first through via, wherein a width of the bond pad is greater than a width of the first through via, wherein the first insulating bonding layer is fused to a second insulating bonding layer of the second device structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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