DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 2 as shown in fig. 4c (claims 1-7, 9-12, 14, 15, 21-25 readable thereon; claims 8 and 13 withdrawn) in the reply filed on 5/29/2026 is acknowledged.
Claim Objections
Claim 9 is objected to because of the following informalities: claim 9 recites “nanos=wire” which appears to include some typographical errors. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Basker et al. (US PGPub 2014/0231891; hereinafter “Basker”).
Re claim 1: Basker teaches (e.g. figs. 4A-5B, 8A, 8B, and 9) a semiconductor device, comprising: an active region (Si fin 206; e.g. paragraph 37); a deposited capacitor material (DCM) layer (TiN layer 208; e.g. paragraph 37) over the active region (206), wherein the DCM layer (208) includes a metal (TiN layer 208; e.g. paragraph 37), a silicide, or a 2-dimensional material; a gate dielectric layer (dielectric 210 such as HfO2; e.g. paragraph 37) over the DCM layer (208); a gate electrode layer (TiN layer 212; e.g. paragraph 37) over the gate dielectric layer (210); and a dielectric material (BOX layer 204 or dielectric spacer 218; e.g. paragraphs 35 and 41) interfacing the DCM layer (208).
Re claim 2: Basker teaches the semiconductor device of claim 1, wherein the 2-dimensional material is graphene or MoS2 (since claim 1 does not require 2-dimensional material, this claim is optional and not required).
Re claim 3: Basker teaches the semiconductor device of claim 1, wherein the gate dielectric layer (210) includes a high-k gate dielectric layer (dielectric 210 such as HfO2; e.g. paragraph 37) between the DCM layer (208) and the gate electrode layer (212).
Re claim 4: Basker teaches the semiconductor device of claim 3, wherein the gate dielectric layer (210) includes an interfacial layer between the high-k gate dielectric layer (dielectric 210 such as HfO2; e.g. paragraph 37) and between the DCM layer (208).
Re claim 5: Basker teaches the semiconductor device of claim 1, wherein the active region (206) is a channel nanowire (fin is approximately 20nm wide and is considered a nanowire since it is nanometer scale and is isolated from the bulk semiconductor substrate by the BOX 204), and wherein the DCM layer (208) fully separates the gate dielectric layer (210) from the channel nanowire (206).
Re claim 6: Basker teaches the semiconductor device of claim 1, wherein the dielectric material (218) is a spacer (spacer 218; e.g. paragraph 41) disposed on a surface of the active region (206).
Re claim 7: Basker teaches the semiconductor device of claim 1, wherein the active region (206) includes a layer of semiconductor material (upper portion of 206) suspended between two source/drain (S/D) regions (source and drain regions 220; e.g. paragraph 42), wherein the DCM layer (208) wraps around (208 wraps around 206) a portion of the layer of the semiconductor material (upper portion of 206).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 9-12, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bangsaruntip et al. (US PGPub 2014/0209864; hereinafter “Bangsaruntip”) in view of Doyle et al. (US PGPub 2008/0237675; hereinafter “Doyle”).
Re claim 1: Bangsaruntip teaches (e.g. figs. 1A, 8, 9, and 11) a semiconductor device, comprising: an active region (patterned nanowire as shown in fig. 1A and 8; e.g. paragraph 50; hereinafter “AR”); a gate dielectric layer (silicon dioxide gate dielectric 802 and high-k dielectric 804 such as HfO2; e.g. paragraphs 52) over the active region (AR); a gate electrode layer (gate material 806; e.g. paragraph 52) over the gate dielectric layer (802, 804); and a dielectric material (sidewall spacer as shown in fig. 1A; hereinafter “DM”) interfacing the active region (AR).
Bangsaruntip is silent as to explicitly teaching a deposited capacitor material (DCM) layer over the active region, wherein the DCM layer includes a metal, a silicide, or a 2-dimensional material; a gate dielectric layer over the DCM layer, and a dielectric material interfacing the DCM layer.
Doyle teaches (e.g. fig. 1) a deposited capacitor material (DCM) layer (electrically conducting layer 140; e.g. paragraph 20) over the active region (semiconductor fin 130; e.g. paragraph 14 of Doyle/AR of Bangsaruntip), wherein the DCM layer (140) includes a metal (TiN, TaN layer 140; e.g. paragraph 20), a silicide, or a 2-dimensional material; the gate dielectric layer (dielectric 150 such as HfO2; e.g. paragraph 16) over the DCM layer (140), and a dielectric material (sidewall spacer DM of Bangsaruntip) interfacing (the combined teachings would have resulted in the DCM layer 140 surrounding AR of Bangsaruntip which would interface with spacer DM of Bangsaruntip) the DCM layer (140).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the metallic layer between the active layer and the capacitor dielectric as taught by Doyle in the device of Bangsaruntip in order to have the predictable result of using metallic electrodes for the both electrodes of the capacitor such that resistance can be minimized for the capacitor structure, thereby improving device performance.
Re claim 3: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 1, wherein the gate dielectric layer (802, 804 of Bangsaruntip) includes a high-k gate dielectric layer (high-k dielectric 804 such as HfO2; e.g. paragraph 52) between the DCM layer (140 of Doyle) and the gate electrode layer (806 of Bangsaruntip).
Re claim 4: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 3, wherein the gate dielectric layer (802, 804 of Bangsaruntip) includes an interfacial layer (silicon dioxide 802; e.g. paragraph 52) between the high-k gate dielectric layer (high-k dielectric 804 such as HfO2; e.g. paragraph 52 of Bangsaruntip) and between the DCM layer (140 of Doyle).
Re claim 9: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 1, wherein the active region (AR) includes an uppermost nanowire (uppermost AR of Bangsaruntip) of a semiconductor material, wherein the DCM layer (140 of Doyle) interfaces a top surface and a bottom surface (bottom surface AR of Bangsaruntip) of the uppermost nanos=wire (uppermost surface AR of Bangsaruntip) of semiconductor material.
Re claim 10: Cheng teaches (e.g. figs. 1A, 8, 9, and 11) a semiconductor structure, comprising: a device (capacitor region as shown in fig. 9; e.g. paragraph 42) over an active region of a substrate (202), wherein the device includes a first source/drain (S/D) region (left-most pad of capacitor region as shown in fig. 5; hereinafter “1SDR”), a first channel region (nanowire closest to a viewer when looking at fig. 5; hereinafter “1CR”) of a semiconductor material extending between the first S/D region (1SDR) and a second S/D region (right-most pad of capacitor region as shown in fig. 5; hereinafter “2SDR”); and a second channel region (nanowire furthest to a viewer when looking at fig. 5; hereinafter “2CR”) of the semiconductor material disposed below (when device of fig. 11 is tilted, 2CR would be below 1CR) the first channel region (1CR).
Bangsaruntip is silent as to explicitly teaching a capacitor material layer over and interfacing the first channel region; wherein the capacitor material is disposed between the first channel region and the second channel region.
Doyle teaches (e.g. fig. 1) a capacitor material layer electrically conducting layer 140; e.g. paragraph 20) over and interfacing the first channel region (semiconductor fin 130; e.g. paragraph 14 of Doyle /1CR of Bangsaruntip); wherein the capacitor material (140) is disposed between (since 140 would surround 1CR and 2CR of Bangsaruntip, 140 would be between 1CR and 2CR) the first channel region (1CR of Bangsaruntip) and the second channel region (2CR of Bangsaruntip).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the metallic layer between the active layer and the capacitor dielectric as taught by Doyle in the device of Bangsaruntip in order to have the predictable result of using metallic electrodes for the both electrodes of the capacitor such that resistance can be minimized for the capacitor structure, thereby improving device performance.
Re claim 11: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 10, wherein the device further includes a gate dielectric layer (802,804 of Bangsaruntip/150 of Doyle) over the capacitor material layer (140 of Doyle).
Re claim 12: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 10, wherein the capacitor material layer (140 of Doyle) wraps around a portion of the second channel region (2CR of Bangsaruntip).
Re claim 14: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 10, wherein the device further includes a gate structure (806 of Bangsaruntip) over the active region (202 of Bangsaruntip) and the first channel region (1CR of Bangsaruntip).
Re claim 15: Bangsaruntip in view of Doyle teaches the semiconductor device of claim 10, wherein the spacer elements (902a of Bangsaruntip) abut the gate structure (806 of Bangsaruntip) and interface the capacitor material layer (140 of Doyle).
Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bangsaruntip et al. (US PGPub 2014/0209864; hereinafter “Bangsaruntip”) in view of Cheng et al. (US PGPub 2018/0083046; hereinafter “Cheng”) and Doyle et al. (US PGPub 2008/0237675; hereinafter “Doyle”).
Re claim 21: Bangsaruntip teaches (e.g. figs. 1A, 8, 9, and 11) teaches a semiconductor device comprising: providing a nanostructure providing channel layers (patterned nanowire as shown in fig. 1A and 8; e.g. paragraph 50; hereinafter “CL”); a gate dielectric layer (silicon dioxide gate dielectric 802 and high-k dielectric 804 such as HfO2; e.g. paragraphs 52) on the channel layer (CL); and a metal gate electrode (gate material 806; e.g. paragraph 52) on the gate dielectric layer (802, 804).
Bangsaruntip is silent as to the nanostructure being a stack of nanostructures; a capacitor material surrounding each channel layer of the stack of nanostructures, wherein the capacitor material includes one of a semiconductor material or a conductive material; a gate dielectric layer on the capacitor material and uppermost channel layer.
Cheng teaches (e.g. fig. 15) a stack of nanostructures (capacitor nanosheets 108, 110, 112; e.g. paragraph 36) and having an uppermost channel layer (108).
Doyle teaches (e.g. fig. 1) a capacitor material (electrically conducting layer 140; e.g. paragraph 20) surrounding each channel layer (CL of Bangsaruntip) of the stack of nanostructures (108, 110, 112 of Cheng), wherein the capacitor material (140) includes one of a semiconductor material or a conductive material (TiN, TaN layer 140; e.g. paragraph 20 of Doyle); a gate dielectric layer (gate dielectric 150; e.g. paragraph 18 of Doyle/802,804 of Bangsaruntip) on the capacitor material (140 of Doyle) and uppermost channel layer (108 of Cheng).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the stack of nanostructures used for the capacitor as taught by Cheng and to use the metallic layer between the active layer and the capacitor dielectric as taught by Doyle in the device of Bangsaruntip in order to have the predictable result of increasing capacitance of the device, and in order to have the predictable result of using metallic electrodes for the both electrodes of the capacitor such that resistance can be minimized for the capacitor structure, thereby improving device performance, respectively.
Re claim 22: Bangsaruntip in view of Cheng and Doyle teaches the semiconductor device of claim 21, further comprising: a spacer layer (spacer as shown in fig. 1A of Bangsaruntip) abutting the capacitor material (140 of Doyle) and over the uppermost channel layer (108 of Cheng).
Re claim 23: Bangsaruntip in view of Cheng and Doyle teaches the semiconductor device of claim 21, wherein, in a cross-sectional view, the capacitor layer (140 of Doyle) interposes the spacer layer (spacer as shown in fig. 1A of Bangsaruntip) and the gate dielectric layer (802, 804 of Bangsaruntip).
Re claim 24: Bangsaruntip in view of Cheng and Doyle teaches the semiconductor device of claim 21, wherein the capacitor material (140 of Doyle) is at least one of a metal (TiN, TaN layer 140; e.g. paragraph 20 of Doyle), a silicide, or a 2-dimensional material and the gate dielectric material is a high-k material (silicon dioxide gate dielectric 802 and high-k dielectric 804 such as HfO2; e.g. paragraphs 52).
Re claim 25: Bangsaruntip in view of Cheng and Doyle teaches the semiconductor device of claim 21, wherein the capacitor material (140 of Doyle) fills a space between a first channel layer (112 of Cheng) of the stack of nanostructures providing channel layers and a second channel layer (110 of Cheng) of the stack of nanostructures providing channel layers (since the combined teachings of the references would have formed capacitor material 140 of Doyle before forming the gate dielectric materials and 140 would have been formed to fill a space between the stacked nanostructures of Cheng).
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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