DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/26/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 3-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,2 and 4-6 of U.S. Patent No. 11,664,286. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons:
Regarding claim 1 of the pending application, US Patent teaches a semiconductor device (see claim 1’s preamble) comprising:
a first semiconductor fin and a second semiconductor fin (refer to a first semiconductor fin and a second semiconductor fin in line 13 col. 17);
an isolation region disposed between the first semiconductor fin and the second semiconductor fin (see col. 17, lines 14-15);
a dummy fin (refer to insulating fin) extending upwards from the isolation region, wherein the dummy fin comprises:
a first dielectric material (refer to the first dielectric material in claim 4) extending from below a topmost surface of the isolation region to above the topmost surface of the isolation region (refer to a first dielectric material in claim 4 as cited line 31-34, col. 17). NOTE: the combination of claims 1 and 2 of the US Patent, the insulating fin extends over and below a top surface of the isolation region. Thus, it would be obvious to one having ordinary skills to understand the first dielectric material extending from below to the top surface of the isolation region; and
a second dielectric material covering a top surface of the first dielectric material (refer to a third dielectric material in claim 7);
a first source/drain region disposed on the first semiconductor fin and physically contacting a first sidewall of the dummy fin; and a second source/drain region disposed on the second semiconductor fin and physically contacting a second sidewall of the dummy fin (see col. 17, lines 19-23).
Regarding claim 3 of the pending application, claim 4 of US Patent teaches the dummy fin further comprises a third dielectric material (refer to a second dielectric material) along sidewalls and a bottom surface of the first dielectric material, wherein the third dielectric material is disposed between the first dielectric material and the isolation region (see claim 4).
Regarding claim 4 of the pending application, US Patent teaches the third dielectric material (refer to the second dielectric material in claim 4) extends along sidewalls of the second dielectric material (refer to the third dielectric material in claim 7). NOTE: since claim 4 of the US Patent claims the second dielectric material lining a sidewall and bottom surface of the first dielectric material and claim 7 of the US Patent claims the third dielectric material on a top surface of the first dielectric material. Thus, it is obviously to one having ordinary skills in the art to understand “the third dielectric material extends along sidewalls of the second dielectric material.”
Regarding claim 5 of the pending application, US Patent teaches similar features as claimed in claim 5.
Regarding claim 6 of the pending application, US Patent teaches similar features as claimed in claim 6.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1,2 and 4 of U.S. Patent No. 11,664,268 in view of Webb (US 2016/0233298).
Regarding claim 2 of the pending application, US Patent teaches all the limitations of the claimed invention for the same reasons as set-forth above. Besides, claim 3 of US Patent teaches a gate stack over and along sidewalls of the insulating fin.
US Patent does not mention the gate stack over and extending along sidewalls of the first semiconductor fin and the second semiconductor fin.
Webb teaches the same field of an endeavor wherein the gate stack (704D/706D) over and extending along sidewalls of the first semiconductor fin (702D) and the second semiconductor fin (702D) (see fig. 7D).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the gate stack over and extending along sidewalls of the first semiconductor fin and the second semiconductor fin as taught by Webb in the teaching of US Patent because it is commonly known in the art the fins act like the transistor’s channel, thus, the gate needs to control the channel electrically.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the dummy fin extends higher than the first semiconductor fin.”
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “a void is disposed between a top surface of the first dielectric material and the isolation region.”
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the second dielectric material is a high-k dielectric material.”
Claims 10-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a device comprising: “wherein the second dielectric material comprises a high-k material; and a gate stack over and along sidewalls of the insulating fin in a second cross-sectional view, wherein the second cross-sectional view is perpendicular to the first cross-sectional view” in combination of all of the limitations of claim 10. Claims 11-14 include all of the limitations of claim 10.
Regarding claim 15, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a method of fabricating a semiconductor device, the method comprising: “recessing the first dielectric film below top surfaces of the semiconductor fins to define a dummy fin, wherein the dummy fin comprises an upper portion of the one or more dielectric materials; forming a gate stack over and along sidewalls of the semiconductor fins and the dummy fin” in combination of all of the limitations of claim 15. Claims 16-20 include all of the limitations of claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
Prosecution Insights