DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/26/2024 and on 12/16/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,087,642. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,087,642 recites all of the limitations in claim 1 of the instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,087,642. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 12,087,642 recites all of the limitations in claim 3 of the instant application.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,087,642. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,087,642 recites all of the limitations in claim 4 of the instant application.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 12,087,642. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of U.S. Patent No. 12,087,642 recites all of the limitations in claim 6 of the instant application.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,676,868. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 11,676,868 recites all of the limitations in claim 14 of the instant application. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 11,676,868. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 11,676,868 recites all of the limitations in claim 15 of the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thareja et al. (2020/0258997). Re claim 1, Thareja teaches a method (Figs. 1-3), comprising: forming, under at least partial vacuum [27, 43], a p-type metal silicide layer (222) on a p-type [24] source/drain region (208) of a semiconductor device (200); and forming, without breaking the at least partial vacuum [27, 43], an n-type metal silicide layer (222) on a n-type [24] source/drain region (208) of the semiconductor device (200). Re claim 2, Thareja teaches the method of claim 1, wherein at least one of: the p-type source/drain region (208) is formed in a first recess (207) of a p-type metal oxide semiconductor (PMOS) region [21, 24] of the semiconductor device (200), or the n-type source/drain region (208) is formed in a second recess (207) of a n-type metal oxide semiconductor (NMOS) region [21, 24] of the semiconductor device (200).
Re claim 3, Thareja teaches the method of claim 1, wherein at least one of: the p-type source/drain region [21, 24] is formed between first gate structures [23] of the semiconductor device (200), or the n-type source/drain region [21, 24] is formed between second gate structures [23] of the semiconductor device (200).
Re claim 4, Thareja teaches the method of claim 1, further comprising: performing, under an at least partial vacuum [26-27, 43], a pre-clean operation to clean the p-type source/drain region [26].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Thareja et al. (2020/0258997) in view of Thareja et al. (2020/0203481). Re claim 5, Thareja teaches the method of claim 1. Thareja ‘997 does not explicitly teach further comprising: forming, without breaking the at least partial vacuum, a first metal barrier layer on and over the p-type metal silicide layer; and forming, without breaking the at least partial vacuum, a second metal barrier layer on and over the n-type metal silicide layer.
Thareja ‘481 teaches a method (Figs. 1-4), further comprising: forming, without breaking the at least partial vacuum [18, 55], a first metal barrier layer (227, [40]) on and over the p-type metal silicide layer (222, [22, 24]); and forming, without breaking the at least partial vacuum [18, 55], a second metal barrier layer (227, [40]) on and over the n-type metal silicide layer (222, [22, 24]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Thareja ‘997 as taught by Thareja ‘481 since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Claim(s) 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over Thareja et al. (2020/0258997) in view of Thareja et al. (2020/0203481).
Re claim 6, Thareja teaches a method (Figs. 1-3), comprising: forming, under at least partial vacuum [27, 43], at least one of a p-type metal silicide layer (222), on a p-type [24] source/drain region (208) of a substrate (202), or an n-type metal silicide layer (222) on a n-type [24] source/drain region (208) of the substrate (202). Thareja ‘997 does not explicitly teach forming, without breaking the at least partial vacuum, at least one of a first metal barrier layer, on the p-type metal silicide layer, or a second metal barrier layer on the n-type metal silicide layer.
Thareja ‘481 teaches a method (Figs. 1-4), teach forming, without breaking the at least partial vacuum [18, 5], at least one of a first metal barrier layer (227, [40]), on the p-type metal silicide layer (222, [22, 24]), or a second metal barrier layer (227, [40]) on the n-type metal silicide layer (222, [22, 24]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Thareja ‘997 as taught by Thareja ‘481 since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made. Re claim 7, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 6, further comprising forming at least one of a first source/drain contact (226, Thareja ‘481), over the p-type metal silicide layer (222, Thareja ‘481) and the first metal barrier layer (227, Thareja ‘481), or a second source/drain contact (226, Thareja ‘481) over the n-type metal silicide layer (222, Thareja ‘481) and the second metal barrier layer (227, Thareja ‘481).
Re claim 8, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 6, wherein the at least one of: the p-type source/drain region is formed in a first recess of a p-type metal oxide semiconductor (PMOS) region ([21, 24], Thareja ‘997) of a semiconductor device (200, Thareja ‘997), or the n-type source/drain region is formed in a second recess of a n-type metal oxide semiconductor (NMOS) region ([21, 24], Thareja ‘997) of the semiconductor device (200, Thareja ‘997).
Re claim 9, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 8, wherein the at least one of: the p-type source/drain region is formed in a bottom of the first recess (207, Thareja ‘997), or the n-type source/drain region is formed in a bottom of the second recess (207, Thareja ‘997).
Re claim 10, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 8, wherein the at least one of: the first metal barrier layer (227, Thareja ‘481) is formed in the first recess (207, Thareja ‘997), or the second metal barrier layer (227, Thareja ‘481) is formed in the second recess (207, Thareja ‘997). Re claim 11, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 8, wherein the at least one of: the first metal barrier layer is formed on a side of the first recess, or the second metal barrier layer (227, Thareja ‘481) is formed in a side (“top side”) of the second recess (207, Thareja ‘997). Re claim 12, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 6, wherein the at least one of: the p-type source/drain region (208, Thareja ‘997) is formed between first gate structures ([23], Thareja ‘997) of a semiconductor device (200, Thareja ‘997), or the n-type source/drain region (227, Thareja ‘481) is formed between second gate structures ([23], Thareja ‘997) of the semiconductor device (200, Thareja ‘997).
Re claim 13, Thareja ‘997 in view of Thareja ‘481 teaches the method of claim 12, wherein the at least one of: the first metal barrier layer (227, Thareja ‘481) intersects with at least one of the first gate structures ([19, 25], Thareja ‘481), or the second metal barrier layer (227, Thareja ‘481) intersects with at least one of the second gate structures ([19, 25], Thareja ‘481).
Prior art of record
Re claim 14, Thareja et al. (2020/0258997) teaches a method (Figs. 1-3), comprising: forming, under at least partial vacuum [27, 43], a p-type metal silicide layer (222) on a p-type [24] source/drain region (208) of a substrate (202). Thareja does not explicitly teach forming, without breaking the at least partial vacuum, an n-type metal silicide layer on the p-type metal silicide layer; and forming, without breaking the at least partial vacuum, a source/drain contact over the n-type metal silicide layer.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the method of claim 14, including each of the limitations and specifically forming, without breaking the at least partial vacuum, an n-type metal silicide layer on the p-type metal silicide layer; and forming, without breaking the at least partial vacuum, a source/drain contact over the n-type metal silicide layer, for the same reasons as mentioned for claim 14 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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