DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/26/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,074,207. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '207 discloses, in claim 1, a device, comprising: a semiconductor nanostructure over a substrate; and a gate structure over and laterally surrounding the semiconductor nanostructure, the gate structure including: a first dielectric layer including a first dielectric material having dopants, wherein a greatest concentration of the dopants decreases as a distance to the semiconductor nanostructure decreases; a second dielectric layer on the first dielectric layer; and a metal layer over the second dielectric layer (all limitations are the same with the limitations recited in claim 1 of Pat '207).
Regarding claim 2, Pat '207 discloses the device of claim 1 as described above.
Pat '207 further discloses, in claim 2, the greatest concentration of the dopants decreases as a distance from the metal layer increases (all limitations are the same with the limitations recited in claim 2 of Pat '207).
Regarding claim 3, Pat '207 discloses the device of claim 1 as described above.
Pat '207 further discloses, in claim 3, the dopants include at least one of ions of lanthanum, magnesium, yttrium, titanium, aluminum, niobium or boron (all limitations are the same with the limitations recited in claim 3 of Pat '207).
Regarding claim 4, Pat '207 discloses the device of claim 1 as described above.
Pat '207 further discloses, in claim 4, the gate structure further comprises: a work function metal layer between the second dielectric layer and the metal layer; and a work function barrier layer between the work function metal layer and the second dielectric layer (all limitations are the same with the limitations recited in claim 4 of Pat '207).
Regarding claim 5, Pat '207 discloses the device of claim 4 as described above.
Pat '207 further discloses, in claim 5, the work function barrier layer comprises at least one of TiN, WN, MoN, or TaN (all limitations are the same with the limitations recited in claim 5 of Pat '207).
Regarding claim 6, Pat '207 discloses the device of claim 1 as described above.
Pat '207 further discloses, in claim 6, the gate structure further comprises: a work function metal layer between the second dielectric layer and the metal layer; a first interfacial layer between the first dielectric layer and the semiconductor nanostructure; and a second interfacial layer between the work function metal layer and the second dielectric layer (all limitations are the same with the limitations recited in claim 6 of Pat '207).
Regarding claim 7, Pat '207 discloses the device of claim 1 as described above.
Pat '207 further discloses, in claim 7, the gate structure further comprises: a work function metal layer between the second dielectric layer and the metal layer; a first interfacial layer between the first dielectric layer and the semiconductor nanostructure; and a second interfacial layer between the work function metal layer and the second dielectric layer (all limitations are the same with the limitations recited in claim 7 of Pat '207).
Regarding claim 8, Pat '207 discloses, in claim 8, a device, comprising: a first gate structure including: a first dielectric layer comprising a first dielectric material including dopants, wherein a greatest concentration of the dopants decreases as a distance to a semiconductor nanostructure decreases; a second dielectric layer on the first dielectric layer; and a first metal layer over the second dielectric layer; and a second gate structure including: a third dielectric layer; a fourth dielectric layer on the third dielectric layer; and a second metal layer over the fourth dielectric layer (all limitations are the same with the limitations recited in claim 8 of Pat '207).
Regarding claim 9, Pat '207 discloses the device of claim 8 as described above.
Pat '207 further discloses, in claim 9, the dopants include at least one of ions of lanthanum, magnesium, yttrium, titanium, aluminum, niobium or boron (all limitations are the same with the limitations recited in claim 9 of Pat '207).
Regarding claim 10, Pat '207 discloses the device of claim 8 as described above.
Pat '207 further discloses, in claim 10, a third gate structure including: a fifth dielectric layer having a fifth dielectric material; a sixth dielectric layer over the fifth dielectric layer; and a third metal layer over the sixth dielectric layer; wherein concentration of dopants in the fifth dielectric material is different than the concentration of dopants in the first dielectric material (all limitations are the same with the limitations recited in claim 10 of Pat '207).
Regarding claim 11, Pat '207 discloses the device of claim 10 as described above.
Pat '207 further discloses, in claim 11, the first gate structure further comprises a first work function metal layer between the second dielectric layer and the first metal layer; the second gate structure further comprises a second work function metal layer having substantially the same composition as the first work function metal layer, the second work function metal layer being between the fourth dielectric layer and the second metal layer; and the third gate structure further comprises: a third work function metal layer having substantially the same composition as the first work function metal layer, the third work function metal layer being between the sixth dielectric layer and the third metal fill layer; and a work function barrier layer between the third work function metal layer and the sixth dielectric layer (all limitations are the same with the limitations recited in claim 11 of Pat '207).
Regarding claim 12, Pat '207 discloses the device of claim 11 as described above.
Pat '207 further discloses, in claim 12, the first work function metal layer includes: an N-type work function metal layer; an in-situ capping layer on the N-type work function metal layer; and an oxygen blocking layer on the in-situ capping layer (all limitations are the same with the limitations recited in claim 12 of Pat '207).
Regarding claim 13, Pat '207 discloses the device of claim 11 as described above.
Pat '207 further discloses, in claim 13, the first gate structure further comprises an interfacial layer between the first work function metal layer and the second dielectric layer, the interfacial layer comprising TiSiNO (all limitations are the same with the limitations recited in claim 13 of Pat '207).
Regarding claim 14, Pat '207 discloses, in claim 14, a method, comprising: forming a first tuning dielectric layer over a first dielectric layer, wherein the first dielectric layer is over a plurality of semiconductor channels associated with corresponding gate structures; removing the first tuning dielectric layer over a first subset of the plurality of semiconductor channels; forming a second tuning dielectric layer over the first dielectric layer over the plurality of semiconductor channels; removing the second tuning dielectric layer over a second subset of the plurality of semiconductor channels; driving in dopants to the first dielectric layer; removing the first and second tuning dielectric layers over the first dielectric layer; forming a second dielectric layer over the first dielectric layer; and forming a metal layer over the second dielectric layer ("a method, comprising: forming a first tuning dielectric layer over a first dielectric layer, wherein the first dielectric layer is over a first semiconductor nanostructure associated with a first gate structure, a second semiconductor nanostructure associated with a second gate structure and a third semiconductor nanostructure associated with a third gate structure; removing the first tuning dielectric layer over the second semiconductor nanostructure and the third semiconductor nanostructure; forming a second tuning dielectric layer over the first dielectric layer, wherein the second tuning dielectric layer is over the first, second and third semiconductor nanostructures; removing the second tuning dielectric layer over the third semiconductor nanostructure; driving in dopants from the first and second tuning dielectric layers to the first dielectric layer over the first semiconductor nanostructure and from the second tuning dielectric layer to the first dielectric layer over the second semiconductor nanostructure; removing the first and second tuning dielectric layers over the first dielectric layer; forming a second dielectric layer over the first dielectric layer; and forming a metal layer over the second dielectric layer", in claim 14 of Pat '207, is interpreted as the same limitation).
Regarding claim 15, Pat '207 discloses the method of claim 14 as described above.
Pat '207 further discloses, in claim 15, forming a work function barrier layer over the second dielectric layer before the forming a metal layer; and forming a work function metal layer over the work function barrier layer before the forming a metal layer (all limitations are the same with the limitations recited in claim 15 of Pat '207).
Regarding claim 16, Pat '207 discloses the method of claim 14 as described above.
Pat '207 further discloses, in claim 16, forming a first interfacial layer on at least the first subset of semiconductor channels before the forming a first tuning dielectric layer; and forming a second interfacial layer on the second dielectric layer before the forming a metal layer ("forming a first interfacial layer on the first semiconductor nanostructure and the second semiconductor nanostructure before the forming a first tuning dielectric layer; and forming a second interfacial layer on the second dielectric layer before the forming a metal layer", in claim 16 of Pat '207, is interpreted as the same limitation).
Regarding claim 17, Pat '207 discloses the method of claim 16 as described above.
Pat '207 further discloses, in claim 17, the forming a second interfacial layer includes: forming a high-k capping layer on the second dielectric layer; forming the second interfacial layer by a thermal anneal performed on the high-k capping layer; and removing the high-k capping layer by an artificial-intelligence-controlled atomic layer etch process (all limitations are the same with the limitations recited in claim 17 of Pat '207).
Regarding claim 18, Pat '207 discloses the method of claim 14 as described above.
Pat '207 further discloses, in claim 18, the forming a second tuning dielectric layer is after the removing a first tuning dielectric layer and before the driving in the dopants (all limitations are the same with the limitations recited in claim 18 of Pat '207).
Regarding claim 19, Pat '207 discloses the method of claim 14 as described above.
Pat '207 further discloses, in claim 19, forming a work function metal layer over the second dielectric layer before the forming a metal layer, including: forming an N-type work function metal layer; forming an in-situ capping layer on the N-type work function metal layer; and forming an oxygen blocking layer on the in-situ capping layer (all limitations are the same with the limitations recited in claim 19 of Pat '207).
Regarding claim 20, Pat '207 discloses the method of claim 19 as described above.
Pat '207 further discloses, in claim 20, forming a glue layer on the work function metal layer; and wherein the metal layer is formed on the glue layer (all limitations are the same with the limitations recited in claim 20 of Pat '207).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cheng (US 11107736).
Regarding claim 1, Cheng discloses, in at least figures 1C, 1E, and related text, a device, comprising:
a semiconductor nanostructure (120B, col. 5/ lines 7-41) over a substrate (106, col. 5/ lines 7-41); and
a gate structure (112P1-112P4, col. 6/ line 24- col. 7/ line 51) over and laterally surrounding the semiconductor nanostructure (120B, col. 5/ lines 7-41), the gate structure (112P1-112P4, col. 6/ line 24- col. 7/ line 51) including:
a first dielectric layer (127, col. 6/ line 24- col. 7/ line 51) including a first dielectric material having dopants (col. 6/ line 24- col. 7/ line 51), wherein a greatest concentration of the dopants decreases as a distance to the semiconductor nanostructure decreases (figures);
a second dielectric layer (128P1-128P4, col. 6/ line 24- col. 7/ line 51) on the first dielectric layer (127, col. 6/ line 24- col. 7/ line 51); and
a metal layer (132, col. 10/ lines 1-43) over the second dielectric layer (128P1-128P4, col. 6/ line 24- col. 7/ line 51).
Regarding claim 2, Cheng discloses the device of claim 1 as described above.
Cheng further discloses, in at least figures 1C, 1E, and related text, the greatest concentration of the dopants decreases as a distance from the metal layer (132, col. 10/ lines 1-43) increases (figures).
Regarding claim 3, Cheng discloses the device of claim 1 as described above.
Cheng further discloses, in at least figures 1C, 1E, and related text, the dopants include at least one of ions of lanthanum (col. 6/ line 24- col. 7/ line 51), magnesium, yttrium (col. 6/ line 24- col. 7/ line 51), titanium, aluminum, niobium or boron.
Regarding claim 7, Cheng discloses the device of claim 1 as described above.
Cheng further discloses, in at least figures 1C, 1E, and related text, the device includes a fin-type field-effect transistor (FinFET) device or a gate-all-around device (col. 3/ lines 58-62).
Regarding claim 8, Cheng discloses, in at least figures 1C, 1E, and related text, a device, comprising:
a first gate structure (112P1, col. 6/ line 24- col. 7/ line 51) including:
a first dielectric layer (127, col. 6/ line 24- col. 7/ line 51) comprising a first dielectric material including dopants (col. 6/ line 24- col. 7/ line 51), wherein a greatest concentration of the dopants decreases as a distance to a semiconductor nanostructure decreases (figures);
a second dielectric layer (128P1, col. 6/ line 24- col. 7/ line 51) on the first dielectric layer (127, col. 6/ line 24- col. 7/ line 51); and
a first metal layer (132, col. 10/ lines 1-43) over the second dielectric layer; and
a second gate structure (112P2, col. 6/ line 24- col. 7/ line 51) including:
a third dielectric layer (127, col. 6/ line 24- col. 7/ line 51);
a fourth dielectric layer (128P2, col. 6/ line 24- col. 7/ line 51) on the third dielectric layer (127, col. 6/ line 24- col. 7/ line 51); and
a second metal layer (132, col. 10/ lines 1-43) over the fourth dielectric layer (128P2, col. 6/ line 24- col. 7/ line 51).
Regarding claim 9, Cheng discloses the device of claim 8 as described above.
Cheng further discloses, in at least figures 1C, 1E, and related text, the dopants include at least one of ions of lanthanum (col. 6/ line 24- col. 7/ line 51), magnesium, yttrium (col. 6/ line 24- col. 7/ line 51), titanium, aluminum, niobium or boron.
Regarding claim 10, Cheng discloses the device of claim 8 as described above.
Cheng further discloses, in at least figures 1C, 1E, and related text, a third gate structure (112P3, col. 6/ line 24- col. 7/ line 51) including:
a fifth dielectric layer (127, col. 6/ line 24- col. 7/ line 51) having a fifth dielectric material;
a sixth dielectric layer (128P3, col. 6/ line 24- col. 7/ line 51) over the fifth dielectric layer (127, col. 6/ line 24- col. 7/ line 51); and
a third metal layer (132, col. 10/ lines 1-43) over the sixth dielectric layer (128P3, col. 6/ line 24- col. 7/ line 51);
wherein concentration of dopants in the fifth dielectric material is different than the concentration of dopants in the first dielectric material (col. 6/ line 24- col. 7/ line 51, figures).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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