Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made the instant application is a continuation of US Patent application 18361429. US Patent application 18361429 is a divisional of US Patent application 17329068. US Patent application 17329068 has a provisional 63168034 filed on 03/30/2021.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites:
“wherein the width of the hole in the at least one of the dielectric layers becomes less than the nominally constant width as a result of the implanting step”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“wherein the width of the hole in the at least one of the dielectric layers becomes less than the nominally constant width as a result of the implanting a dopant species”.
Claims 2-10 depend from claim 1.
Claim 11 recites:
“performing an expansion process on at least a portion of the dielectric layer to cause the portion of the dielectric layer to expand”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“performing an expansion process on at least a portion of the dielectric layer to cause the at least a portion of the dielectric layer to expand”.
Claims 12-16.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-5, 7-8, 11-15, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20200098591 A1 – hereinafter Lin).
Regarding Claim 1, Lin teaches a method of manufacturing a semiconductor device (see the entire document; Fig. 4D(1) in view of Figs. 4A-4E; specifically, ([0039] - [0048]), and as cited below), comprising:
depositing a plurality of dielectric layers (432, 433 – Fig. 4D(1) – [0053]) over a target structure (430 – [0047]);
etching ([0039]) through the plurality of dielectric layers (432U, 433) to form a hole (439 – Fig. 4B(1) – [0040]) extending through the plurality of dielectric layers (432U, 433) and exposing the target structure (430), the hole having a nominally constant width (as shown in Fig. 4B(1)), when viewed in cross section, in each dielectric layer of the plurality of dielectric layers;
implanting a dopant species into at least one of the plurality of dielectric layers to cause the at least one of the plurality of dielectric layers to expand, wherein the width of the hole in the at least one of the dielectric layers becomes less than the nominally constant width as a result of the implanting step ([0048] teaches ion implantation causes layer 432U to expand in a lateral direction (arrow 436)); and
filling the hole with material (440 – [0045]).
Regarding Claim 2, Lin teaches the method of claim 1, wherein: the plurality of dielectric layers includes an etch stop layer and an insulator layer; the step of etching through the plurality of dielectric layers includes a first etch to form the hole in the insulator layer and a second step to extend the hole through the etch stop layer; and the step of implanting a dopant species into at least one of the plurality of dielectric layers includes implanting the dopant species into the insulator layer (see Fig. 4B(2) – [0048]).
Regarding Claim 3, Lin teaches the method of claim 1, wherein after the step of etching through the plurality of dielectric layers to form a hole, the width of the hole deviates from the nominally constant width as a result of etch process variations (as can be seen between Fig. 4B(1) and Fig. 4B(2)).
Regarding Claim 4, Lin teaches the method of claim 1, wherein dopant species is implanted into the at least one of the plurality of dielectric layers uniformly to cause uniform expansion of the at least one of the plurality of dielectric layers from top to bottom of the at least one of the dielectric layers ([0048] teaches ion implants dopants are controllable – hence maybe made uniform).
Regarding Claim 5, Lin teaches the method of claim 1, wherein dopant species is implanted into the at least one of the plurality of dielectric layers with a concentration gradient to cause a gradient of expansion of the at least one of the plurality of dielectric layers from top to bottom of the at least one of the dielectric layers ([0048]).
Regarding Claim 7, Lin teaches the method of claim 1, wherein the step of implanting a dopant species into at least one of the plurality of dielectric layers causes an expansion of the at least one of the plurality of dielectric layers of from 3% to 7% (per [0048], dopant is controllable).
Regarding Claim 8, Lin teaches the method of claim 1, wherein the at least one of the plurality of dielectric layers is silicon oxide and further wherein the dopant species has an atomic radius at least as great as the atomic radius of silicon ([0062] states 432 is silicon dioxide. [0048] state dopant can be germanium. Atomic radius of silicon is 210 pm and that of germanium 211).
Regarding Claim 11, Lin teaches a method of manufacturing a semiconductor device (see the entire document; Fig. 4D(1) in view of Figs. 4A-4E; specifically, ([0039] - [0048]), and as cited below), comprising:
forming a target conductor (430 – [0047] – Fig. 4D(1)) in a layer (432);
forming a dielectric layer (432U) over the target conductor (430) and the layer (432);
patterning the dielectric layer to have a hole (439 – Fig. 4B(1) – [0040]) extending therethrough, the hole nominally aligned to the target conductor (430), wherein the hole has a cross-sectional width (in x-direction);
performing an expansion process on at least a portion of the dielectric layer to cause the portion of the dielectric layer to expand and decrease the cross-sectional width of the hole ([0048] teaches ion implantation causes layer 432U to expand in a lateral direction (arrow 436)); and
filling the hole having the decreased cross-sectional width with a material (440 – [0045]) that makes electrical contact with the target conductor (430 as seen in Fig. 4D(1)).
Regarding Claim 12, Lin teaches the method of claim 11, wherein the step of performing an expansion process comprises implanting a dopant species into the at least a portion of the dielectric layer ([0048]).
Regarding Claim 13, Lin teaches the method of claim 12, wherein the dopant species has an atomic radius at least as great as the atomic radius of silicon ([0062] states 432 is silicon dioxide. [0048] state dopant can be germanium. Atomic radius of silicon is 210 pm and that of germanium 211).
Regarding Claim 14, Lin teaches the method of claim 12, wherein the dopant species is implanted uniformly throughout a thickness of the dielectric layer ([0048] teaches ion implants dopants are controllable – hence maybe made uniform).
Regarding Claim 15, Lin teaches the method of claim 12, wherein the dopant species is implanted with a concentration gradient throughout a thickness of the dielectric layer ([0048]).
Regarding Claim 17, Lin teaches a method of manufacturing a semiconductor device (see the entire document; Fig. 4D(1) in view of Figs. 4A-4E; specifically, ([0039] - [0048]), and as cited below), comprising:
depositing a silicon oxide layer (432U – [0062] – Fig. 4D(1)) over a structure (430 – [0047]);
etching an opening in the silicon oxide layer (432U), the opening (439 – Fig. 4B(1) – [0040]) having a nominal cross-section width;
implanting into the silicon oxide layer a dopant species having an atomic radius at least as great as the atomic radius of silicon to cause the silicon oxide layer to expand and the nominal cross-section width of the opening to decrease ([0048] teaches ion implantation causes layer 432U to expand in a lateral direction (arrow 436)); and
filling the opening with a conductive material (440 – [0045]) electrically contacting the structure (430).
Regarding Claim 18, Lin teaches the method of claim 17, wherein the silicon oxide layer is a material selected from the group consisting of tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicon oxide, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), and boron doped silicon glass (BSG) (Doped – [0048]).
Regarding Claim 19, Lin teaches the method of claim 17, wherein dopant species is selected from the group consisting of Ge, Ar, Xe, Si, and combinations thereof (Ge, Si – [0048]).
Allowable Subject Matter
Claims 6, 9-10, 16, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 6: The method of claim 5, wherein after the step of implanting the dopant species into at least one of the plurality of dielectric layers, the width of the hole increases from a top of the at least one of the dielectric layers to a bottom of the at least one of the plurality of dielectric layers.
Regarding claim 9: The method of claim 1, further comprising: forming a masking layer over the plurality of dielectric layers, the masking layer covering a portion of the at least one of the plurality of dielectric layers, while leaving a second portion of the at least one of the plurality of dielectric layers exposed; and implanting the dopant species into at least one of the plurality of dielectric layers through the masking layer so that only the second portion of the at least one of the plurality of dielectric layers expands.
Claim 10 depends from claim 9.
Regarding claim 16: The method of claim 11, further comprising forming a patterned mask layer over the dielectric layer and wherein the at least a portion of the dielectric layer is defined by the patterned mask layer.
Regarding claim 20: The method of claim 17, wherein after the step of implanting into the silicon oxide layer a dopant species the cross-section width of the opening decreases from a bottom of the silicon oxide layer to a top of the silicon oxide layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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