Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12299371.
Current Application # 18785611
US Pat # 12299371
For example:
Claim1:
A method of placing dummy cells in an integrated circuit, comprising: acquiring descriptions of functional blocks that include layout data on the functional blocks; spacing the functional blocks based on the descriptions of the functional blocks; and inserting dummy cells and/or dummy cell markers next to the functional blocks based on the descriptions of the functional blocks.
For example:
Claim 1:
A device, comprising: functional blocks including a first functional block and a second functional block; and dummy cells, each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a first dummy cell having a first top edge and a first bottom edge situated between the first functional block and the second functional block such that the first dummy cell directly abuts each of the first functional block and the second functional block where the first top edge of the first dummy cell is situated next to a second bottom edge of the first functional block without leaving space between the first dummy cell and the first functional block and the first bottom edge of the first dummy cell is situated next to a second top edge of the second functional block without leaving space between the first dummy cell and the see functional block.
4. The device of claim 1, wherein the first functional block includes a layout pattern, and the second functional block includes the layout pattern.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “descriptions of the functional blocks” in current application 18785611 and the limitation “top edge of the second functional block ” in US Pat # 12299371 are not identical but overall scope of the claims are identical and they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US Pub # 2021/0042461).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Hu et al. teach a method of placing dummy cells in an integrated circuit, comprising: acquiring descriptions of functional blocks that include layout data on the functional blocks (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, functional block 85, 85_1, dummy cells 20/25); spacing the functional blocks based on the descriptions of the functional blocks; and inserting dummy cells and/or dummy cell markers next to the functional blocks based on the descriptions of the functional blocks (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, marker 70/75).
Even though Hu et al. teach dummy cells block and normal block but silent exclusively about functional block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hu et al. where memory block includes dummy cells and memory block includes normal functioning cells which would be called functional block in order to minimize device degradation during manufacturing including minimizing defects (see paragraph 0002).
Regarding claim 2, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells and/or dummy cell markers at edges of a first functional block to fit the first functional block within a second functional block blocks (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0078).
Regarding claim 3, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells at edges of a first functional block to abut the dummy cells with the first functional block and a second functional block (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0079).
Regarding claim 4, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells and/or dummy cell markers between two functional blocks of the functional blocks to directly abut one or more dummy cells to each of the two functional blocks (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071).
Regarding claim 5, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells in locations indicated by the dummy cell markers (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0068).
Regarding claim 6, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach , wherein acquiring descriptions of functional blocks that include layout data on the functional blocks includes acquiring functions performed by the functional blocks (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077).
Regarding claim 7, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, wherein acquiring descriptions of functional blocks that include layout data on the functional blocks includes acquiring block width, height, active region locations, and gate spacing (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0078).
Regarding claim 8, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells and/or dummy cell markers at edges of a first functional block to fill a gap between the first functional block and a second functional block (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0079).
Regarding independent claim 9, Hu et al. teach a method of placing dummy cells in an integrated circuit, comprising: placing functional blocks in the integrated circuit without having information about layout patterns of the functional blocks; acquiring the layout patterns of the functional blocks placed in the integrated circuit; checking placement of the functional blocks in the integrated circuit based on the layout patterns of the functional blocks and layout rules (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, design rule check DRC in step S140, S250); and moving the functional blocks to have spaces next to at least some of the functional blocks to avoid violating the layout rules, wherein moving the functional blocks configures the spaces to be filled directly by dummy cells or to be marked with dummy cell markers and filled later with dummy cells that correspond to the dummy cell markers (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, functional block 85, 85_1, dummy cells 20/25).
Even though Hu et al. teach dummy cells block and normal block but silent exclusively about functional block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hu et al. where memory block includes dummy cells and memory block includes normal functioning cells which would be called functional block in order to minimize device degradation during manufacturing including minimizing defects (see paragraph 0002).
Regarding claim 10, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, comprising inserting pattern bridge cells, that match the layout patterns of functional blocks next to the spaces, in the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071).
Regarding claim 11, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, comprising inserting asymmetric dummy cells, that match the layout patterns of functional blocks next to the spaces, in the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0065).
Regarding claim 12, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, wherein placing functional blocks in the integrated circuit includes placing standard logic cells and/or macros in the integrated circuit (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071).
Regarding claim 13, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, wherein, immediately after placing functional blocks in the integrated circuit, the method includes checking whether placement of the functional blocks in the integrated circuit satisfies floorplan layout rules (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077).
Regarding claim 14, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, comprising inserting a dummy cell, that is configured to beinserted between an SRAM block and a functional block, in one of the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0070).
Regarding claim 15, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hu et al. further teach, comprising inserting a dummy cell, that is configured to be inserted between a first macro and a second macro, in one of the spaces, wherein one side of the dummy cell directly abuts the first macro, and another side of the dummy cell directly abuts the second macro (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0078).
Regarding independent claim 16, Hu et al. teach a method of placing dummy cells in an integrated circuit, comprising: placing functional blocks in the integrated circuit without having information about layout patterns of the functional blocks; acquiring the layout patterns of the functional blocks placed in the integrated circuit; checking placement of the functional blocks in the integrated circuit based on the layout patterns of the functional blocks and layout rules (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, design rule check DRC in step S140, S250); moving the functional blocks to have spaces next to at least some of the functional blocks to avoid violating the layout rules; and inserting dummy cell markers in the spaces as placeholders for dummy cells (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080, functional block 85, 85_1, dummy cells 20/25).
Even though Hu et al. teach dummy cells block and normal block but silent exclusively about functional block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hu et al. where memory block includes dummy cells and memory block includes normal functioning cells which would be called functional block in order to minimize device degradation during manufacturing including minimizing defects (see paragraph 0002).
Regarding claim 17, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Hu et al. further teach, comprising inserting dummy cells that correspond to the dummy cell markers in the spaces in place of the dummy cell markers (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071).
Regarding claim 18, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Hu et al. further teach, comprising inserting a dummy cell marker, that is configured to be inserted between an SRAM block and a functional block, in one of the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077).
Regarding claim 19, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Hu et al. further teach, comprising inserting a dummy cell marker, that is configured to be inserted between a first macro and a second macro, in one of the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0078).
Regarding claim 20, Hu et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Hu et al. further teach, comprising inserting a dummy cell marker, that is configured to be inserted between a macro and a functional block, in one of the spaces (see Fig. 1-8, 10-15 and paragraph 0028-0059, 0061-0071, 0077-0080).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824