DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “wherein the first device includes a first channel member and a first gate dielectric layer disposed over the first channel member, the first gate dielectric layer including a first dipole material from a first dipole layer and a second dipole material from a second dipole layer,
wherein the second device includes a second channel member and a second gate dielectric layer disposed over the second channel member, the second gate dielectric layer including the first dipole material from the first dipole layer but not the second dipole material from the second dipole layer,
wherein the third device includes a third channel member and a third gate dielectric layer disposed over the third channel member, the third gate dielectric layer including the second dipole material from the second dipole layer but not the first dipole material from the first dipole layer, and
wherein the fourth device includes a fourth channel member and a fourth gate dielectric layer disposed over the fourth channel member, the fourth gate dielectric layer not including the first dipole material from the first dipole layer or the second dipole material from the second dipole layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin).
Regarding Claim 10: Nakjin discloses a semiconductor device (see Nakjin, Figs.2E-2G and 3 as shown below and ¶ [0002]), comprising:
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a semiconductor substrate (100) (see Nakjin, Figs.2E-2G as shown above);
a first stack of channel layers (SP1/CH3) and a second stack of channel layers (SP1/CH4) on the semiconductor substrate (100) (see Nakjin, Figs.2E-2G as shown above);
a first gate dielectric layer (GI2) surrounding layers of the first stack of channel layers (SP1/CH3), the first gate dielectric layer (GI2) including a p-type dipole material (aluminum (Al)) (see Nakjin, Figs.2E-2G and 3 as shown above and ¶ [0071]);
a second gate dielectric layer (GI2) surrounding layers of the second stack of channel layers (SP/CH4), the second gate dielectric layer (GI2) including an n-type dipole material (lanthanum (La)) (see Nakjin, Figs.2E-2G and 3 as shown above and ¶ [0071]); and
a gate electrode (GE2) on the first gate dielectric layer (GI2) and on the second gate dielectric layer (GI2) (see Nakjin, Figs.2E-2G and 3 as shown above).
Regarding Claim 11: Nakjin discloses a semiconductor device as set forth in claim 10 as above. Nakjin further teaches wherein the p-type dipole material is aluminum oxide, and the n-type dipole material is lanthanum oxide (see Nakjin, Figs.2E-2G and 3 as shown above, ¶ [0071], and ¶ [0110]- ¶ [0111]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin) in view of Chen et al. (U.S. 2019/0318967 A1, hereinafter refer to Chen).
Regarding Claim 1: Nakjin discloses a semiconductor structure (see Nakjin, Figs.2E-2G and 3 as shown above and ¶ [0002]), comprising:
a stack of nanostructures (SP) (see Nakjin, Figs.2E-2G as shown above);
an interfacial layer (IL) wrapping around each nanostructure (SP) of the stack of nanostructures (SP) (see Nakjin, Figs.2E-2G as shown above);
a first gate dielectric layer (HK) wrapping around the interfacial layer (IL) and each nanostructure of the stack of nanostructures (SP) (see Nakjin, Figs.2E-2G as shown above); and
a gate electrode layer (GE) disposed over the first gate dielectric layer (HK) (see Nakjin, Figs.2E-2G as shown above),
wherein the first gate dielectric layer (HK) includes a dipole element (see Nakjin, Figs.2E-2G as shown above and ¶ [0070]- ¶ [0072]).
Nakjin is silent upon explicitly disclosing wherein a first concentration of the dipole element at a center line of the first gate dielectric layer is greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer interfacing the interfacial layer.
For support see Chen, which teaches wherein a first concentration of the dipole element (602/604) at a center line of the first gate dielectric layer (600) is greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer (600) interfacing the interfacial layer (80) (see Chen, Figs.21-23 and 25 as shown below and ¶ [0067]- ¶ [0078]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Nakjin and Chen to enable first concentration of the dipole element at a center line of the first gate dielectric layer to be greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer interfacing the interfacial layer as taught by Chen in order to alter or tune threshold voltages of the transistor devices.
Regarding Claim 2: Nakjin as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Nakjin and Chen further teaches wherein the first gate dielectric layer (Fig.25, 600/Fig.21, 82) includes an oxidized metal element (metal oxide) (see Chen, Figs.21-23 and 25 as shown below and ¶ [0040]).
The combination of Nakjin and Chen is silent upon explicitly disclosing wherein a first ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer is about 1:8 to about 1:3.
However, the combination of Nakjin and Chen teaches identical metal oxide dielectric material doped with dipole element as the claimed invention as shown in Chen, ¶ [0067]- ¶ [0078]; hence,
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer through routine experimentation and optimization to obtain optimal or desired threshold voltages because the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s composition, does not render the old composition patentably new to the discoverer.
Regarding Claim 3: Nakjin as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Nakjin and Chen further teaches wherein the first gate dielectric layer (Fig.25, 600/Fig.21, 82) includes an oxidized metal element (metal oxide) (see Chen, Figs.21-23 and 25 as shown below and ¶ [0040]).
The combination of Nakjin and Chen is silent upon explicitly disclosing wherein a second ratio of a concentration of the dipole element to a concentration of the metal element at the boundary surface of the first gate dielectric layer is about 1:4 to about 1:1.5.
However, the combination of Nakjin and Chen teaches identical metal oxide dielectric material doped with dipole element as the claimed invention as shown in Chen, ¶ [0067]- ¶ [0078]; hence,
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer through routine experimentation and optimization to obtain optimal or desired threshold voltages because the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s composition, does not render the old composition patentably new to the discoverer.
Regarding Claim 4: Nakjin as modified teaches a semiconductor structure as set forth in claim 3 as above. The combination of Nakjin and Chen further teaches wherein the boundary surface of the first gate dielectric layer (Fig.25, 600/Fig.21, 82) is a first boundary surface (see Chen, Figs.21-23 and 25 as shown below and ¶ [0040]).
The combination of Nakjin and Chen is silent upon explicitly disclosing wherein a third ratio of a concentration of the dipole element to a concentration of the metal element at a second boundary surface of the first gate dielectric layer opposing the first boundary surface is about 1:4 to about 1:1.5.
However, the combination of Nakjin and Chen teaches identical metal oxide dielectric material doped with dipole element as the claimed invention as shown in Chen, ¶ [0067]- ¶ [0078]; hence,
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer through routine experimentation and optimization to obtain optimal or desired threshold voltages because the ratio of a concentration of the dipole element to a concentration of the metal element at the center line of the first gate dielectric layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s composition, does not render the old composition patentably new to the discoverer.
Regarding Claim 5: Nakjin as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Nakjin and Chen further teaches wherein the dipole element includes a p-type dipole element (aluminum (Al)) (see Nakjin, ¶ [0030] and ¶ [0065] and see Chen, ¶ [0067]).
Regarding Claim 6: Nakjin as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Nakjin and Chen further teaches wherein the interfacial layer (80) includes the dipole element, and wherein a third concentration of the dipole element in the interfacial layer (80) is less than the second concentration (see Chen, Figs.21-23 and 25 as shown above and ¶ [0067]- ¶ [0078]).
Regarding Claim 7: Nakjin as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Nakjin and Chen further teaches a second gate dielectric layer (one or more barrier) wrapping around the first gate dielectric layer (Fig.25, 600/Fig.22, 150/152/154) (see Chen, Figs.21-22 and 25 as shown above and ¶ [0052]); and
a capping layer (conformal layers 106 includes one or more barrier and/or capping layers and one or more work-function tuning layers) wrapping around the second gate dielectric layer (conformal layers 106 includes one or more barrier) (see Chen, Fig.22 as shown above and ¶ [0052]),
wherein the gate electrode layer (108) wraps around the capping layer (conformal layers 106 includes one or more capping layers) (see Chen, Fig.22 as shown above and ¶ [0052]).
Regarding Claim 8: Nakjin as modified teaches a semiconductor structure as set forth in claim 7 as above. The combination of Nakjin and Chen further teaches wherein the capping layer includes titanium nitride, tantalum nitride, or a combination thereof (see Chen, Fig.22 as shown above and ¶ [0052]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin) and Chen et al. (U.S. 2019/0318967 A1, hereinafter refer to Chen) as applied to claim 1 above, and further in view of Yang et al. (U.S. 2020/0373300 A1, hereinafter refer to Yang).
Regarding Claim 9: Nakjin as modified teaches a semiconductor structure as applied to claim 1 above. The combination of Nakjin and Chen is silent upon explicitly disclosing wherein a first dielectric fin and a second dielectric fin sandwiching the stack of nanostructures, and
wherein a lateral distance from the first gate dielectric layer to the first dielectric fin and the second dielectric fin is about 4 nm to about 13 nm.
For support see Yang, which teaches wherein a first dielectric fin (150C) and a second dielectric fin (150a/150b) sandwiching the stack of nanostructures (NSS) (see Yang, Figs.2-9 and ¶ [0064]), and
wherein a lateral distance (D11/D12) from the first gate dielectric layer (152) to the first dielectric fin (150c) and the second dielectric fin (150A/150B) (see Yang, Figs.2-9 and ¶ [0064]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Nakjin, Chen, and Yang to enable the first dielectric fin and the second dielectric fin sandwiching the stack of nanostructures, a lateral distance from the first gate dielectric layer to the first dielectric fin and the second dielectric fin as taught by Yang in order to enhance of the performance and reliability of the transistors.
The combination of Nakjin, Chen, and Yang is silent upon explicitly disclosing wherein a lateral distance from the first gate dielectric layer to the first dielectric fin and the second dielectric fin is about 4 nm to about 13 nm.
However, the combination of Nakjin, Chen, and Yang teaches wherein a lateral distance (D11/D12) from the first gate dielectric layer (152) to the first dielectric fin (150c) and the second dielectric fin (150A/150B) (see Yang, Figs.2-9 and ¶ [0064]); hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the lateral distance from the first gate dielectric layer to the first dielectric fin and the second dielectric fin through routine experimentation and optimization to obtain optimal or desired device performance and reliability because the lateral distance from the first gate dielectric layer to the first dielectric fin and the second dielectric fin is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin).
Regarding Claim 12: Nakjin discloses a semiconductor device as applied to claim 10 above. Nakjin further teaches wherein the first gate dielectric layer (GI2) includes hafnium oxide (see Nakjin, Figs.2E-2G as shown above, ¶ [0040], and ¶ [0071]).
Nakjin is silent upon explicitly disclosing wherein a ratio of a concentration of aluminum to a concentration of hafnium in the first gate dielectric layer is about 1:3 to about 1:2 at a surface of the first gate dielectric layer.
However, Nakjin teaches doping aluminum into the hafnium oxide gate dielectric layer (HK) (see Nakjin, Figs.2E-2G as shown above, ¶ [0040], and ¶ [0071]); hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the concentration of aluminum to a concentration of hafnium in the first gate dielectric layer through routine experimentation and optimization to obtain optimal or desired threshold voltage because the concentration of aluminum to a concentration of hafnium in the first gate dielectric layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s composition, does not render the old composition patentably new to the discoverer.
Regarding Claim 13: Nakjin discloses a semiconductor device as applied to claim 10 above. Nakjin further teaches wherein the first gate dielectric layer (GI2) includes a gate dielectric material (HK) having a first metal element, and the p-type dipole material includes a second metal element, and a ratio of a concentration of the second metal element (aluminum) to the first metal element (HK) (see Nakjin, Figs.2E-2G as shown above, ¶ [0040], and ¶ [0071]).
Nakjin is silent upon explicitly disclosing wherein a ratio of a concentration of the second metal element to the first metal element is about 1:6 to about 1:4 at a middle thickness of the first gate dielectric layer.
However, Nakjin teaches doping aluminum into the hafnium oxide gate dielectric layer (HK) (see Nakjin, Figs.2E-2G as shown above, ¶ [0040], and ¶ [0071]); hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the concentration of aluminum to a concentration of hafnium in the first gate dielectric layer through routine experimentation and optimization to obtain optimal or desired threshold voltage because the concentration of aluminum to a concentration of hafnium in the first gate dielectric layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s composition, does not render the old composition patentably new to the discoverer.
Claim(s) 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin) in view of Zhang et al. (U.S. 2022/0199796 A1, hereinafter refer to Zhang).
Regarding Claim 14: Nakjin discloses a semiconductor structure (see Nakjin, Figs.2E-2G and 3 as shown above, Figs.1 and 2C as shown below and ¶ [0002]), comprising:
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a first device (PER), a second device (LGC, NR), a third device (LGC, PR), and a fourth device (LGC, NR) (see Nakjin, Figs.1, 2C, 2E-2G and 3 as shown above),
wherein the first device (PER) includes a first channel member and a first gate dielectric layer (GI1) disposed over the first channel member (CH1 or CH2), the first gate dielectric layer (GI1) including a first dipole material from a first dipole layer (DPL1) and a second dipole material from a second dipole layer (DPL2) (note: the first gate insulating layer GI1 includes lanthanum (La) and aluminum (Al)) (see Nakjin, Figs.1, 2C and 3 as shown above and ¶ [0114]- ¶ [0115]),
wherein the second device (LGC, NR) includes a second channel member (CH4) and a second gate dielectric layer (GI2) disposed over the second channel member (CH4), the second gate dielectric layer (GI2) including the first dipole material (lanthanum (La)) from the first dipole layer (DPL1) but not the second dipole material (aluminum (Al)) from the second dipole layer (DPL2) (see Nakjin, Figs.2E-2G and 3 as shown above, ¶ [0070]- ¶ [0072], and ¶ [0114]- ¶ [0115]),
wherein the third device (LGC, PR) includes a third channel member (CH3) and a third gate dielectric layer (GI2) disposed over the third channel member (CH3), the third gate dielectric layer (GI2) including the second dipole material (aluminum (Al)) from the second dipole layer (DPL2) but not the first dipole material (lanthanum (La)) from the first dipole layer (DPL1) (see Nakjin, Figs.2E-2G and 3 as shown above, ¶ [0070]- ¶ [0072], and ¶ [0114]- ¶ [0115].
Nakjin is silent upon explicitly disclosing one or more device include dipole material and one or more device not including dipole material wherein the fourth device includes a fourth channel member and a fourth gate dielectric layer disposed over the fourth channel member, the fourth gate dielectric layer not including the first dipole material from the first dipole layer or the second dipole material from the second dipole layer.
For support see Zhang, which teaches one or more device (structure B) include dipole material and one or more device (structure A) not including dipole material wherein the fourth device (structure A) includes a fourth channel member and a fourth gate dielectric layer (32) disposed over the fourth channel member, the fourth gate dielectric layer (32) not including the first dipole material from the first dipole layer (34) or the second dipole material from the second dipole layer (34) (see Zhang, Figs.11-13 as shown below, ¶ [0029], and ¶ [0074]- ¶ [0087]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Nakjin and Zhang to enable the Nakjin device to include one or more device to include dipole material and one or more device not including dipole material wherein the fourth device includes a fourth channel member and a fourth gate dielectric layer disposed over the fourth channel member, the fourth gate dielectric layer not including the first dipole material from the first dipole layer or the second dipole material from the second dipole layer as taught by Zhang in order to produce a device having various different threshold voltages.
Regarding Claim 15: Nakjin as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Nakjin and Zhang further teaches wherein the first channel member (CH1 or CH2) and the second channel member (CH4) are of different shapes or different dimensions (see Nakjin, Figs.1, 2C, and 2E-2G as shown above).
Regarding Claim 16: Nakjin as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Nakjin and Zhang is silent upon explicitly disclosing wherein the first dipole layer and the second dipole layer are of different thicknesses; however, the combination of Nakjin and Zhang teaches wherein the first dipole layer (DPL1) and the second dipole layer (DPL2) are the same thicknesses (see Nakjin, Figs.7 and 16 and ¶ [0114]- ¶ [0115]).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness of the first dipole layer and the second dipole layer through routine experimentation and optimization to obtain optimal or desired device performance because the the first dipole layer and the second dipole layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 17: Nakjin as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Nakjin and Zhang further teaches wherein the first device, the second device, the third device, and the fourth device have different threshold voltages (see Nakjin, Figs.1, 2C, and 2E-2G as shown above).
Regarding Claim 18: Nakjin as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Nakjin and Zhang further teaches wherein a fifth gate dielectric layer (HK) disposed over the first gate dielectric layer (IL), the second gate dielectric layer (IL), the third gate dielectric layer (IL), and the fourth gate dielectric layer (IL) (see Nakjin, Figs.1, 2C, and 2E-2G as shown above); and
a gate electrode layer (GE) disposed over the fifth gate dielectric layer (HK) (see Nakjin, Figs.1, 2C, and 2E-2G as shown above).
Regarding Claim 20: Nakjin as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Nakjin and Zhang further teaches wherein the first channel member (CH1 or CH2) includes a nanostructure (see Nakjin, Figs.1 and 2C as shown above),
wherein the first gate dielectric layer (GI1) wraps around the first channel member (CH1 or CH2) (see Nakjin, Figs.1 and 2C as shown above), and
wherein the first device further includes a gate electrode layer (GE1) wrapping around the first gate dielectric layer (GI1) (see Nakjin, Figs.1 and 2C as shown above).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nakjin et al. (U.S. 2021/0126102 A1, hereinafter refer to Nakjin) and Zhang et al. (U.S. 2022/0199796 A1, hereinafter refer to Zhang) as applied to claim 18 above, and further in view of Chen et al. (U.S. 2019/0318967 A1, hereinafter refer to Chen).
Regarding Claim 19: Nakjin as modified teaches a semiconductor structure as applied to claim 18 above. The combination of Nakjin and Zhang is silent upon explicitly disclosing wherein a capping layer disposed between the fifth gate dielectric layer and the gate electrode layer.
For support see Chen, which teaches a capping layer (conformal layers 106 includes one or more barrier and/or capping layers and one or more work-function tuning layers) disposed between the fifth gate dielectric layer (conformal layers 106 includes one or more barrier) and the gate electrode layer (108) (see Chen, Figs.21-22 and 25 as shown above and ¶ [0052]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Nakjin, Zhang, and Chen to enable the capping layer disposed between the fifth gate dielectric layer and the gate electrode layer as taught by Chen in order to prevent gate electrode metal diffusion into the dielectric layers.
Conclusion
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/BITEW A DINKE/ Primary Examiner, Art Unit 2812
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