DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/2024 and 11/5/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-4 and 6-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of Hsu et al. U.S. Patent No. 11515403. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
Re claim 1, claim of Hsu teaches a method comprising:
forming a dielectric material (claim 1) over a first source/drain region (claim 1) and a second source/drain region (claim 1);
forming a first gate structure (claim 1) and a second gate structure (claim 1) adjacent the first source/drain region (claim 1) and the second source/drain region (claim 1), respectively, the first gate structure having a first width (claim 1), the second gate structure having a second width (claim 1) that is different from the first width;
depositing a first filling layer (claim 1) over the first gate structure, the second gate structure, and the dielectric material;
performing a first planarization process on the first filling layer (claim 1); and
performing a second planarization process on the first filling layer (claim 1), the second planarization process being different from the first planarization process (claim 1), a top surface of the first filling layer being substantially level with a top surface of the dielectric material after the second planarization process (claim 1).
Re claim 2, claim of Hsu teaches the method of claim 1, wherein the first planarization process is a chemical mechanical polish process (claim 1).
Re claim 3, claim of Hsu teaches the method of claim 2, wherein the first filling layer acts as a stop layer for the chemical mechanical polish process (claim 1).
Re claim 4, claim of Hsu teaches the method of claim 1, wherein the second planarization process is an etch-back process (claim 1).
Re claim 6, claim of Hsu teaches the method of claim 1, further comprising: depositing a second filling layer (claim 1) over the first filling layer before performing the first planarization process, wherein the first planarization process is also performed on the second filling layer (claim 1).
Re claim 7, claim of Hsu teaches the method of claim 1, wherein the first planarization process thins the first filling layer (claim 1), the first filling layer remaining over the first gate structure, the second gate structure, and the dielectric material after the first planarization process (claim 1).
Re claim 8, claim of Hsu teaches a method comprising:
forming a first gate structure (claim 15) and a second gate structure (claim 15) over a substrate, the first gate structure having a first width (claim 15), the second gate structure having a second width that is different from the first width (claim 15);
depositing a first filling layer (claim 15) over the first gate structure and the second gate structure, the first filling layer comprising a first material (claim 15);
depositing a second filling layer (claim 15) over the first filling layer, the second filling layer comprising a second material that is different from the first material (claim 20) ;
performing a first planarization process on the second filling layer (claim 15), the first planarization process being selective to the second material relative to the first material (claim 15); and
performing a second planarization process on the first filling layer and the second filling layer (claim 15), the second planarization process being non-selective between the first material and the second material (claim 15).
Re claim 9, claim of Hsu teaches the method of claim 8, wherein the first material is silicon (claim 20) and the second material is silicon nitride (claim 20).
Re claim 10, claim of Hsu teaches the method of claim 9, wherein the first planarization process is a chemical mechanical polish process (claim 1, 11).
Re claim 11, claim of Hsu teaches the method of claim 9, wherein the second planarization process is a dry etch performed with NF3 and H2 (claim 17).
Re claim 12, claim of Hsu teaches the method of claim 8, further comprising forming an opening in the first filling layer between the first gate structure and the second gate structure before depositing the second filling layer (claim 15).
Re claim 13, claim of Hsu teaches the method of claim 8, wherein the second planarization process is stopped while the first filling layer remains over the first gate structure and the second gate structure (claim 15).
Re claim 14, claim of Hsu teaches a method comprising:
forming a first gate structure (claim 15) and a second gate structure (claim15);
depositing a first filling layer (claim 15) over the first gate structure and the second gate structure;
patterning the first filling layer with an opening (claim 15) between the first gate structure and the second gate structure;
depositing a second filling layer (claim 15) in the opening and over the first filling layer;
performing a first planarization process (claim 15) on the second filling layer to remove an excess portion of the second filling layer over the first filling layer, a remaining portion of the second filling layer in the opening forming an isolation feature between the first gate structure and the second gate structure (claim 15); and
performing a second planarization process (claim 15) on the first filling layer and the isolation feature, a top surface of the first filling layer being level with a top surface of the isolation feature after the second planarization process (claim 15).
Claims 1-5 and 7 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of Hsu et al. U.S. Patent No. 12237402. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
Re claim 1, claim of Hsu teaches a method comprising:
forming a dielectric material (claim 8) over a first source/drain region (claim 8) and a second source/drain region (claim 8);
forming a first gate structure (claim 8) and a second gate structure (claim 8) adjacent the first source/drain region (claim 8) and the second source/drain region (claim 8), respectively, the first gate structure having a first width (claim 8), the second gate structure having a second width (claim 81) that is different from the first width;
depositing a first filling layer (claim 8) over the first gate structure, the second gate structure, and the dielectric material;
performing a first planarization process on the first filling layer (claim 8); and
performing a second planarization process on the first filling layer (claim 8), the second planarization process being different from the first planarization process (claim 8), a top surface of the first filling layer being substantially level with a top surface of the dielectric material after the second planarization process (claim 8).
Re claim 2, claim of Hsu teaches the method of claim 1, wherein the first planarization process is a chemical mechanical polish process (claim 8).
Re claim 3, claim of Hsu teaches the method of claim 2, wherein the first filling layer acts as a stop layer for the chemical mechanical polish process (claim 8).
Re claim 4, claim of Hsu teaches the method of claim 1, wherein the second planarization process is an etch-back process (claim 8).
Re claim 5, claim of Hsu teaches the method of claim 4, wherein the etch-back process etches the first filling layer and the dielectric material at substantially the same rate (claim 8).
Re claim 7, claim of Hsu teaches the method of claim 1, wherein the first planarization process thins the first filling layer (claim 8), the first filling layer remaining over the first gate structure, the second gate structure, and the dielectric material after the first planarization process (claim 8).
Allowable Subject Matter
Claims 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and with a timely filed terminal disclaimer to overcome the current nonstatutory double patenting rejection.
Specifically, the limitations are material to the inventive concept of the application in hand to achieve more uniform shapes and sizes for devices with different active region density.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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