Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita [US PGPUB 20160079252] in view of Van Houdt et al. [US PGPUB 20180233512] (hereinafter Van Houdt).
Regarding claim 1, Yamashita teaches a method comprising:
providing a substrate (10, Para 22, Fig. 4);
depositing a multi-layer stack (12/102/103/104, Fig.4), at least one layer of the multi-layer stack being a sacrificial layer (i.e., sacrificial layer 102 due to it being etched to form recess 106 (Fig. 7));
etching a trench or via (MH, Para 44) in the multi-layer stack (Fig. 5);
after etching the trench or via (Fig. 5-7), selectively etching the sacrificial layer relative to other materials of the multi-layer stack (Para 45) to form at least one space (106, Para 45) between layers of the multi-layer stack (Fig. 7); and
depositing metal (111, Para 46/47/136/137, Fig. 8/9) comprising tungsten or molybdenum (Para 136/137) in the at least one space to form a metal-containing multi-layer stack having a trench or via etched therein (Fig. 9).
In the method steps of Fig. 4-9 of Yamashita’s invention, Yamashita does not specifically disclose that the substrate is a semiconductor substrate; and
the multi-layer stack is a metal free multi-layer stack having at least three different materials.
However, it is noted that Yamashita discloses that layer 12 is silicon oxide (Para 33), layer 103 is silicon (Para 43), layer 104 is silicon (Para 43), and layer 102 is silicon oxide (SiN).
In view of such teaching, Yamashita discloses two different materials for layer 102. In view of such disclosure, the material of layer 102 is unclear because of the ambiguity in the teaching of layer 102 being silicon oxide (SiN). It could be assumed that SiN in the disclosed "silicon oxide (SiN)" is an error and it should be SiO. However, the error could be that the silicon oxide should read silicon nitride.
In view of such ambiguity, a person having ordinary skills in the art will find it necessary to determine a suitable material for layer 102. Since there are only two options, silicon oxide or silicon nitride, a person having ordinary skills in the art will find it "Obvious to try" - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (MPEP 2143.I.E). It should be noted that either silicon oxide or silicon nitride would be suitable material for layer 102 since it would have a different etch rate from layers 103 and 104.
However, upon further consideration, it seems that it would be obvious to a person having ordinary skills in the art to use silicon nitride for layer 102 because of the disclosure of Yamashita (Para 53), where material 103 and 104 are removed before the removal of layer 102. That is, upon the removal of layer 103 and 104, layer 102 is exposed to layer 12 (silicon oxide layer).
It should be noted that if both layers (12 and 102) are silicon oxide material, there is a tendency of unintentionally etching layer 12 during the etching of layer 102. Thus, it would seem obvious to use silicon nitride for layer 102 instead of silicon oxide to avoid unintentionally etching of layer 12 which could lead to defects in the device being made (MPEP 2143.I.G).
Therefore, with the obviousness of using silicon nitride for layer 102, Yamashita obviously teaches a metal-free multi-layer stack having at least three different materials.
Referring to the invention of Van Houdt, Van Houdt teaches forming a memory device wherein the substrate 100 of the device can be one of multiple types of substrates to include a semiconductor substrate (Para 50).
In view of such teaching by Van Houdt, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the substrate of Yamashita be a semiconductor substrate, at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 2, Yamashita as analyzed teaches a method wherein the sacrificial layer is selected from the group consisting of polysilicon and silicon nitride (silicon nitride).
Regarding claim 12, Yamashita teaches a method comprising:
providing a substrate (10, Para 22, Fig. 4);
depositing a multi-layer stack (16 (102/103/104), Fig. 4) of alternating sacrificial layer (102, due to it being etched to form recess 106 (Fig. 7)) and non-oxide layers (103/104, Si layers, Para 43);
etching a trench or via (MH, Para 44) in the multi-layer stack of alternating sacrificial layer and non- oxide layers (Fig. 5);
after etching the trench (Fig. 5-7), selectively etching sacrificial layer to form spaces (106, Para 46) between the non-oxide layers (Fig. 7); and
depositing metal (111, Para 46/47/136/137) in the spaces to form a substrate comprising the trench etched in alternating metal and non-oxide layers and at least one dielectric barrier layer (barrier layer 12, Fig. 9).
In the method steps of Fig. 4-9 of Yamashita’s invention, Yamashita does not specifically disclose that the substrate is a semiconductor substrate; and
that the sacrificial layer is silicon nitride layer.
However, it is noted that Yamashita discloses that layer 102 is silicon oxide (SiN).
In view of such teaching, Yamashita discloses two different materials for layer 102. In view of such disclosure, the material of layer 102 is unclear because of the ambiguity in the teaching of layer 102 being silicon oxide (SiN). It could be assumed that SiN in the disclosed "silicon oxide (SiN)" is an error and it should be SiO. However, the error could be that the silicon oxide should read silicon nitride.
In view of such ambiguity, a person having ordinary skills in the art will find it necessary to determine a suitable material for layer 102. Since there are only two options, silicon oxide or silicon nitride, a person having ordinary skills in the art will find it "Obvious to try" - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (MPEP 2143.I.E). It should be noted that either silicon oxide or silicon nitride would be suitable material for layer 102 since it would have a different etch rate from layers 103 and 104.
However, upon further consideration, it seems that it would be obvious to a person having ordinary skills in the art to use silicon nitride for layer 102 because of the disclosure of Yamashita (Para 53), where material 103 and 104 are removed before the removal of layer 102. That is, upon the removal of layer 103 and 104, layer 102 is exposed to layer 12 (silicon oxide layer).
It should be noted that if both layers (12 and 102) are silicon oxide material, there is a tendency of unintentionally etching layer 12 during the etching of layer 102. Thus, it would seem obvious to use silicon nitride for layer 102 instead of silicon oxide to avoid unintentionally etching of layer 12 which could lead to defects in the device being made (MPEP 2143.I.G).
Therefore, with the obviousness of using silicon nitride for layer 102, Yamashita obviously teaches a metal-free multi-layer stack having at least three different materials.
Referring to the invention of Van Houdt, Van Houdt teaches forming a memory device wherein the substrate 100 of the device can be one of multiple types of substrates to include a semiconductor substrate (Para 50).
In view of such teaching by Van Houdt, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the substrate of Yamashita be a semiconductor substrate, at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 18, Yamashita teaches a method wherein the metal comprises tungsten (Para 136/137).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Van Houdt and further in view of Asami [US PGPUB 20090283812].
Regarding claim 19, the combined invention of Yamashita and Van Houdt teaches the limitation of claim 12 upon which it depends.
The combined inventions do not specifically disclose where the metal comprises molybdenum.
Referring to the invention of Asami, Asami discloses numerous known materials used for floating gates of a memory device (claim 5), wherein some materials overlap with the list of Yamashita, wherein the material could further comprise molybdenum.
In view of such teaching by Asami, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined inventions comprise the teaching of Asami at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Allowable Subject Matter
Claims 3-11, 13-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISMAIL A MUSE whose telephone number is (571)272-1470. The examiner can normally be reached Monday - Friday 8:00 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571)270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ISMAIL A MUSE/Primary Examiner, Art Unit 2812
Prosecution Insights