Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 17
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 7/26/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Integrated circuit with two arrays and interface in-between that outputs analog voltage to second array.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11837281. Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare independent claims from both set, we find that they recite the same claim limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hoang et al. (US 20210397931).
Regarding independent claim 1, Hoang discloses an integrated circuit (Figs. 1-15), comprising:
a first array of resistors (Fig. 12 shows NVM array 1201. Examiner asserts that array of memory means array of resistors);
a second array of resistors (Fig. 12 shows NVM array 1201. Examiner asserts that array of memory means array of resistors); and
a plurality of interface circuits electrically coupled between the first array of resistors and the second array of resistors (Fig. 12 shows DAC 1213 and 1214. Along with ADC 1231, sigmoid 1232 etc., together these circuits form interface circuits. [0073] describes that each of arrays 1201, 1203, and 1205 is of size (m+n)xn, where the (m+n)xn memory cells are connected along (m+n) word lines and n bit lines),
wherein each interface circuit among the plurality of interface circuits is configured to
receive a signal from the first array of resistors (Fig. 12 shows DAC 1213 and 1214 receiving input from first array 1201), and
apply an analog voltage corresponding to the signal to the second array of resistors (Fig. 12 and [0074] describes that x.sub.t values are digital values that are converted to corresponding analog voltages by one or more digital to analog converters (DACs) before being fed to second array 1203).
Regarding claim 3, Hoang discloses all the elements of claim 1 as above and further at least one resistor among the resistors in the first array or the second array is a memory cell ([0073] describes three non-volatile memory arrays: array 1201 for the weights W.sub.r, array 1203 for the weights W.sub.z, and array 1205 for the weights W.sub.h).
Regarding claim 4, Hoang discloses all the elements of claim 1 as above and further the first array of resistors and the second array of resistors configure a neural network (Fig. 12 and [0073] describes an architecture for a GRU-based process-in-memory RNN (recurrent neural network) inference accelerator).
Regarding claim 5, Hoang discloses all the elements of claim 4 as above and further the second array of resistors comprises an output layer of the neural network, and the integrated circuit further comprises a plurality of analog-to-digital converter (ADC) circuits electrically coupled to output conductive lines of the second array of resistors (Fig. 12 and [0075] describes that output along the bit lines of each of array 1201, 1203, and 1205 is received at a corresponding analog to digital converter (ADC) 1231, 1233, and 1235, where the digital outputs are in turn input into a corresponding activation function).
Regarding claim 6, Hoang discloses all the elements of claim 4 as above and further a third array of resistors; and a plurality of further interface circuits electrically coupled between the second array of resistors and the third array of resistors, wherein each further interface circuit among the plurality of further interface circuits is configured to receive a further signal from the second array of resistors, and apply a further analog voltage corresponding to the further signal to the third array of resistors (Fig. 12 shows three array and two interface circuits connected as prescribed).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hoang et al. (US 20210397931) in view of Bergman et al. (US 20020114146).
Regarding claim 2, Hoang discloses all the elements of claim 1 as above and through Bergman further at least one resistor among the resistors in the first array or the second array is a controllably variable resistor ([0031] describes resistor array with controllable variable resistance).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Bergman to modified Hoang in order to provide with resistor network that is capable of being controlled by the control circuitry as taught by Bergman ([0006]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hoang et al. (US 20210397931) in view of Batra.
Regarding claim 7, Hoang discloses all the elements of claim 1 as above and through Batra further said each interface circuit among the plurality of interface circuits comprises: an integrator circuit configured to receive the signal, and integrate the signal over time to generate an intermediate voltage, and a buffer circuit electrically coupled to the integrator circuit to receive the intermediate voltage, and configured to generate the analog voltage corresponding to the intermediate voltage (Fig. 2 and (5)-(8) describes circuit 21 where each signal line is connected to the interface circuit. The integrator 23a provides an output voltage that is proportional to the length of time. And comparators 25a and 26a receives input from previous stage integrator).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Batra to modified Hoang in order to provide with high throughput data transfer technique as taught by Batra ((2)).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 11139843) in view of Hoang et al. (US 20210397931).
Regarding independent claim 17, Li discloses an integrated circuit (Figs. 1-6), comprising:
a first array of resistors (Fig. 4 shows resistors 404 through 410);
a second array of resistors (Fig. 4 shows resistors 414 through 420); and
at least one interface circuit electrically coupled between the first array of resistors and the second array of resistors,
wherein the at least one interface circuit comprises (Fig. 4 shows in-between circuitry that constitutes interface):
an operational amplifier (402; Fig. 4) having
a first input electrically coupled to the first array of resistors (Fig. 4 shows vref connected to first resistor array),
a second input (vfb; Fig. 4), and
an output (Fig. 4 shows output of 402);
a transistor (M7 and M8; Fig. 4) having
a gate terminal electrically coupled to the output of the operational amplifier (Fig. 4 shows that gates of M7 and M8 being connected to output of 402),
a first source/drain terminal electrically coupled to the second array of resistors (Fig. 4 shows that one of S/D terminal being electrically connected to second resistor array), and
a second source/drain terminal electrically coupled to a node of a power supply voltage (Fig. 4 shows that the other of S/D terminal being connected to VDD); and
a feedback circuit electrically coupled between the first source/drain terminal of the transistor and the second input of the operational amplifier (Fig. 4 shows feedback path vfb).
Hoang teaches a first array of resistors (Fig. 12 shows NVM array 1201. Examiner asserts that array of memory means array of resistors);
a second array of resistors (Fig. 12 shows NVM array 1201. Examiner asserts that array of memory means array of resistors);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hoang to Li in order to reduce the amount of data transfer needed to perform inferencing operations for a recurrent neural network, or RNN, as taught by Hoang ([0019]).
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 5/20/2026
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