DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a silicide layer in a portion of the dummy layer in contact with the contact structures” of claim 3, the “recessing the gate structure” of claims 10-12, claim 13 and dependent claims must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding the silicide layer of claim 3, the silicide layer (152a) appears to be formed in the source/drain epitaxial layer (comprising 128c) and not “a portion the dummy layer (148) in contact with contact structures (comprising 154 and 156)” in view of fig. 2F.
Regarding “recessing the gate structures” in view of Paragraph 0052 recessing the gate structure appears to occur before fig. 1 and 2A, in addition paragraph explicitly states that the recessing of the gate structure is not shown in “the high-k dielectric layers 136, work function layers 138, and the spacer layers 120 are recessed to form a recess above the gate structure 132 (not shown)”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 recites the limitation “annealing the dummy layer to form a silicide layer”. In view of the specification, it appears that the epitaxial layer is annealed to form a silicide layer and the protection layer protects the dummy layer from the anneal process in paragraphs 0061-0063, nowhere within the specification does it recite the dummy layer is annealed. In view of this no art has been applied to claim 3.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 recite the limitation "the recessed gate structure" in claim 10. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will interpret the limitation as “a recessed gate structure” in claim to establish an antecedent basis.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 12356697 B2 Yoon et al hereafter “Yoon”.
Claim 1 Yoon teaches a method for forming a semiconductor device structure, comprising:
forming nanostructures (NSS fig. 12A-B) over a substrate (102 fig. 12A-B);
forming a gate structure (DP and 114 fig. 13A-C and prior steps, then 160 fig. 16A-D and subsequent figures 13A-16C illustrate a gate replacement process of the gate structure) surrounding and over the nanostructures;
forming spacer layers (118A Fig. 16A-D) over opposite sides of the gate structure over the nanostructures;
forming a dummy layer (118B fig. 16A-D) over sidewalls of the spacer layers [sufficiently illustrated fig. 16A-D];
forming contact structures (174 fig. 17A-C) beside the gate structure;
removing the dummy layer to form an air spacer (AS1 Fig. 18A-D) between the spacer layers and the contact structures [sufficiently illustrated fig. 18A-D]; and
depositing a sealing liner layer (190 and 190P fig. 19A-C) over the gate structure, the contact structure, and the air spacer [sufficiently illustrated fig. 19A-D].
Claim 2 Yoon teaches as shown above the method of claim 1, further comprising:
before the forming of the contact structures, forming a protection layer (118C fig. 16A-C) over sidewalls of the dummy layer [sufficiently illustrated in the steps of fig. 16A-17C],
wherein the air spacer is formed between the spacer layers and the protection layer [sufficiently illustrated fig. 16A-C].
Claim 10 Yoon teaches the method of claim 1, further comprising:
recessing the gate structure after the forming of the spacer layers [illustrated fig. 12A-14D] and
forming a hard mask layer (164 fig. 16A-D, Met under 2112.01 the composition is the same as disclosed “Silicon Nitride” (SiN) Column 11 lines 10-11) over the recessed gate structure [met under broadest reasonable interpretation 164 is over at least part of the gate structure (including 160 fig. 16A-D) that after the gate recessing process].
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Annotated fig. 14B: highlighting part of the recess made
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon as applied to the claims above, and further in view of US 9735047 B1 Chang et al hereafter “Chang”, and US 20150021683 A1 Xie et al here after “Xie”
Claim 4 Yoon teaches as shown above the method of claim 1, further comprising:
Yoon teaches forming a filling film (164 fig. 16A-D) over the gate Structure.
Yoon Does not teach forming the filling film over the seal liner layer; and
depositing a contact etch stop layer over the filling film.
Chang teaches forming a filling film (64 fig. 9) over a seal liner layer (best illustrated as 62 fig. 8, also referred to as “liner” 58 fig. 6 ) for an air gap (60 fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Combine the filling film of Yoon in view of Chang such that the filling film is formed over the seal liner layer.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional insulation and/or masking protection to the gate structure as well as the gate spacers.
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is filling films and/or gate caps/masks for the purpose of insulating and/or protecting the underlying gate structures and/or gate spacers.
Xie teaches depositing a contact etch stop layer (128 fig. 3F) over a filling film (124R fig. 3F) and gate spacers/liners (112 and/or 113 fig. 3F).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoon in view of Chang in further view of Xie such that “depositing a contact etch stop layer over the filling film” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to provide protect the under lying filling film and spacer/liner structures [explicitly disclosed Paragraph 0041 Xie in “The sacrificial etch stop material layer 128 may be comprised of a variety of materials that may be used to protect the recessed gate cap layers 124 and the underlying sidewall spacers 112 when a contact opening is subsequently etched in the layer of insulating material 114”]
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Chang and Xie as applied to the claims above, and in further view of US 20200335336 A1 Leobandung et al hereafter “Leobandung”
Claim 5 Yoon in view of Chang and Xie teaches the method of claim 4.
Yoon in view of Chang and Xie does not teach forming a void in the filling film over the gate structure while forming the filling film.
Leobandung teaches forming a void (709 fig. 9) in a filling film (comprising 911 and 707) over a gate structure (505 and 404 fig. 9) while forming the filling film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Combine the filling film of Yoon in view of Chang and Xie in further view of Leobandung such that “forming a void in the filling film over the gate structure while forming the filling film” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to lower the parasitic capacitance from the gate to adjacent conductive structures [explicitly disclosed 0045 Leobandung in “the gate parasitic cap to contact is lower because there is a void 709 between eventual source drain contact to the gate.”]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is filling films for the purpose of insulating the gate.
Claims 11-15, 13-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon as applied to the claims above, and further in view of Chang.
Claim 11 Yoon teaches as shown above the method of claim 10, wherein the recessing of the gate structure also recesses the spacer layers (sufficiently illustrated fig. 14A-D), and
Yoon does not teach the hard mask layer is formed over top surfaces of the spacer layers.
Chang teaches forming a hard mask layer (64 fig. 9) over a spacer layers (best illustrated as 62 fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Combine the filling film of Yoon in view of Chang such “the hard mask layer is formed over top surfaces of the spacer layers”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional insulation and/or masking protection to the gate structure as well as the gate spacers.
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is filling films and/or gate caps/masks for the purpose of insulating and/or protecting the underlying gate structures and/or gate spacers
Claim 12 Yoon in view of Chang teaches the method of claim 11, wherein after the recessing of the gate structure, a top surface of the spacer layers is substantially level with a top surface of the hard mask layer (sufficiently illustrated 16A-D the top most surfaces of 118B is planar with the top most surface of 164, met under broadest reasonable interpretation steps of fig. 16A-D are after the recessing steps of 13A-14D).
Claim 13 Yoon teaches a method for forming a semiconductor device structure, comprising:
forming one or more semiconductor channels (NSS fig. 12A-D) over a substrate (102 fig. 1233A-D);
forming a gate structure (DP and 114 fig. 12A-D and 160 fig. 16A-D, wherein fig. 13A-16D illustrate a gate replacement process preformed on the gate structure) surrounding and over the one or more semiconductor channels [sufficiently illustrated fig. 12A-D];
forming spacer layers (118A fig. 12A-D) over opposite sides of the gate structure;
recessing the gate structure and the spacer layers (illustrated fig. 13A-14C as part of the gate replacement process) to form a gate trench (GS fig. 14A-D);
forming a hard mask (164 fig. 16A-D) in the gate trench and over the gate structure and gate spacers;
forming a dummy layer (118B fig. 12A-D) over sidewalls of the hard mask and spacer layers;
forming contact structures (174 fig. 17A-C) beside the dummy layer; and
removing the dummy layer (18A-D) to form an air spacer (AS1 fig. 18A-D) between the spacer layers and the contact structures.
Yoon does not teach forming the hard mask over the gate spacers; nor forming a dummy layer over sidewalls of the hard mask
Chang teaches forming a hard mask layer (64 fig. 9) over a spacer layers (best illustrated as 62 fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Combine the filling film of Yoon in view of Chang such “the hard mask layer is formed over top surfaces of the spacer layers”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional insulation and/or masking protection to the gate structure as well as the gate spacers.
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is filling films and/or gate caps/masks for the purpose of insulating and/or protecting the underlying gate structures and/or gate spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoon in view of Chang such that “forming a dummy layer over sidewalls of the hard mask” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to as rearrangement of parts is prima facie type obviousness as rearrangement and/or changes in size is prima facie type obviousness [See MPEP 2144.04 VI C. and/or MPEP 2144.04 IV A.] and/or to enable the hard mask layer being over the spacer layers as modified above.
Claim 14 Yoon in view of Chang teaches as shown above the method of claim 13, further comprising:
depositing a sealing liner layer (190P and 190 fig. 19A-C) over the gate structure, the contact structures, and the air spacer.
Claim 15 Yoon in view of Chang teaches as shown above the method of claim 14, wherein after the depositing of the sealing liner layer, a top surface of the air spacer is substantially level with a top surface of the contact structures [sufficiently illustrated fig. 19A-C the top most surface of the air spacer is substantially level with the top most surface of the contact structures 174, under broadest reasonable interpretation of “substantially” which is includes “being largely but not wholly that which is specified” (websters-dictionary definition 5), the examiner further notes that this “substantially” is a relative term, although not indefinite in the context of the claims].
Claim 18 Yoon teaches as shown above a method for forming a semiconductor device structure, comprising:
forming one or more semiconductor channels (NSS fig. 12A-D) over a substrate (102 fig. 12A-D);
forming source/drain epitaxial features (SD1 and/or SD1 fig. 12A-D) adjacent the one or more semiconductor channels [sufficiently illustrated fig. 12A-D];
forming a gate structure (DP and 114 fig. 12A-D, 160 fig. 16A-D and subsequent figures, fig. 13-16 illustrated a gate replacement process preformed on the gate structure) surrounding and over the one or more semiconductor channels (sufficiently illustrated fig. 12A-D and fig. 16A-D);
forming spacer layers (118A fig. 12A-D) over opposite sides of the gate structure;
forming a hard mask (DC fig. 12A-D) over the gate structure;
forming a dummy layer (118B fig. 12A-D) over sidewalls of the spacer layers;
forming contact structures (174 fig. 17A-C) over the source/drain epitaxial features and beside the dummy layer;
removing the dummy layer (removing the dummy layer 118B illustrated fig. 18A) and the hard mask (removing the hard mask DC illustrated fig. 13A-14D), wherein the removing of the dummy layer forms an air spacer (AS1 fig. 18A-D) between the spacer layers and the contact structures; and
depositing a sealing liner layer (190P and 190 fig. 19A-C) over the gate structure, the contact structure, and the air spacer.
Yoon does not teach forming the hard mask over the gate spacers; nor forming a dummy layer over sidewalls of the hard mask
Chang teaches forming a hard mask layer (64 fig. 9) over a spacer layers (best illustrated as 62 fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Combine the filling film of Yoon in view of Chang such “the hard mask layer is formed over top surfaces of the spacer layers”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional insulation and/or masking protection to the gate structure as well as the gate spacers.
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is filling films and/or gate caps/masks for the purpose of insulating and/or protecting the underlying gate structures and/or gate spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoon in view of Chang such that “forming a dummy layer over sidewalls of the hard mask” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to as rearrangement of parts is prima facie type obviousness as rearrangement and/or changes in size is prima facie type obviousness [See MPEP 2144.04 VI C. and/or MPEP 2144.04 IV A.] and/or to enable the hard mask layer being over the spacer layers as modified above.
Claim 19 Yoon in view of Chang teaches the method of claim 18, further comprising:
before the forming of the contact structures, forming a protection layer (118C fig. 12-D) over sidewalls of the dummy layer,
wherein the air spacer is formed between the spacer layers and the protection layer [sufficiently illustrated fig. 18A-D].
Claims 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Chang as applied to the claims above, and further in view of US 10818498 B1 Shen et al hereafter “Shen”.
Claim 16 Yoon in view of Chang teaches the method of claim 13.
Yoon in view Chang teaches a gate fill metal structure (184 fig. 19C) over the recessed gate structure.
Yoon in view of Chang does not teach depositing the gate fill metal over the recessed gate structure, wherein the hard mask is formed over the gate fill metal.
Shen teaches a gate fill metal (26 fig. 7) over a recessed gate structure (comprising 22 fig. 7), wherein a hard mask (44 fig. 7) is formed over the gate fill metal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoon in view of Chang in further view of Shen such that “the gate fill metal over the recessed gate structure, wherein the hard mask is formed over the gate fill metal”.
A person of ordinary skill in the art would have been motivated to make this modification to protect the gate fill metal from subsequent processing.
In addition, combining and/or substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining/substituting known gate fill metals for the purpose of electrically addressing a recessed gate structure.
Allowable Subject Matter
Claims 6-9, 17, and 20 comprise allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter: Claim 6-7 recites “etching a portion of the source/drain epitaxial structures below the dummy layer” in context of the rest of the claim.
Claim 8-9 recites “removing the hard mask layer when removing the dummy layer” in context of the rest of the claim.
Claim 17 recites “the removing of the dummy layer simultaneously removes the hard mask” in context of the rest of the claim.
Claim 20 recites “removing of the dummy layer includes etching a portion of the source/drain epitaxial features below the dummy layer” in context of the rest of the claim.
Claims 6-9, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
During the course of search the examiner although the examiner found similar prior art as shown above, however the examiner did not find prior art the teaches the limitations as recited above in context of the claims nor obvious reason to modify prior art such that the claim limitation is taught in context of the rest of the claim limitations
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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