DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 and dependent claims are objected to because of the following informalities: Claim 18 and dependent claims recites the antecedent basis for “a first direction” twice once in “each row of the array of semiconductor devices extending in a first direction” in claim 18 and once in “a stack of a plurality of insulating layers and sacrificial layers alternatively stacking on top of each other, and extending in a first direction” in claim 18. The second instance should be corrected such that it reads “the first direction” or establishes a new/different antecedent basis Appropriate correction is required.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 18 are rejected under 35 U.S.C. 102(a)(2) as being by US 11251199 B2 Zhang et al hereafter “Zhang”.
Claim 9 Zhang A method of making a semiconductor device, comprising:
forming a stack (comprising 32 and 42 fig. 3A-3C) of a plurality of insulating layers (32 fig. 3A-3C) and sacrificial layers (42 fig. 3A-3C) alternatively stacking on top of each other [sufficiently illustrated fig. 3A-3C], and extending in a first direction (hd1 fig. 3A-3C);
forming a plurality of gate layers (46 fig. 13A-13C) by replacing the plurality of sacrificial layers [sufficiently illustrated steps of fig. 11A-13C];
forming a memory layer (54 fig. 5A-5C) extending along the first direction and coupled to the plurality of gate layers in a second direction (hd2 fig. 5A-5C) perpendicular to the first direction [sufficiently illustrated fig. 8A-8C];
forming a channel layer (60 fig. 10A-10C) extending along the first direction and coupled to the memory layer in the second direction [sufficiently illustrated fig. 10A-10C]; and
forming a source and a drain (63 and 61 fig. 8A-8C) spaced apart from the source in the first direction [sufficiently illustrated fig. 8A-8C].
Claim 18 Zhang teaches a method of making a semiconductor device, comprising:
forming an array of semiconductor devices (illustrated fig. 16A-16G), each row [sufficiently illustrated fig. 16A-16G] of the array of semiconductor devices extending in a first direction (hd1 fig. 16A-16G), the forming of each semiconductor device comprising:
forming a stack (42 and 32 fig. 3A-3C) of a plurality of insulating layers (32 fig. 3A-3C) and sacrificial layers (42 fig. 3A-3C) alternatively stacking on top of each other, and extending in a first direction ;
forming a plurality of gate layers (46 fig. 13A-13C) by replacing the plurality of sacrificial layers [sufficiently illustrated in the steps of fig. 11A-13C];
forming a memory layer (54 fig. 5A-5C) extending along the first direction and coupled to the plurality of gate layers in a second direction (hd2 fig. 5A-5C) perpendicular to the first direction [sufficiently illustrated fig. 5A-5C];
forming a channel layer (60 fig. 10A-10C) extending along the first direction and coupled to the memory layer in the second direction [sufficiently illustrated fig. 5A-5C]; and
forming a source and a drain (61 and 63 fig. 8A-8C) spaced apart from the source in the first direction [sufficiently illustrated fig. 8A-8C].
Claims 1-2, 6-8, 10-13, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to the claims above, and further in view of US 20190319044 A1 Harari et al hereafter “Harari”
Claim 1 Zhang teaches a method of making a semiconductor device, comprising:
providing a stack (comprising at least 32 and 42 Fig. 3A-3C) comprising a plurality of insulating layers (32 fig. 3A-3C) and a plurality of sacrificial layers (32 and 42 fig. 3A-3C) alternatively stacked on top of each other, the stack extending in a first direction (hd1 fig. 3A-3C
forming a plurality of gate layers (comprising 46 fig. 13A-13C) by replacing the plurality of sacrificial layers [sufficiently illustrated fig. 11A-13C];
forming a memory layer (54 fig. 5A-5C) extending along the first direction radially inwards of and coupled to the plurality of gate layers in a second direction (hd2 fig. 5A-5C) perpendicular to the first direction;
forming a channel layer (60 fig. 10A-10C) extending along the first direction and coupled to a radially inner surface of the memory layer in the second direction [sufficiently illustrated fig. 10A-10C]; and
forming a source and a drain (61 and 63 fig. 8A-8C) spaced apart from the source in the first direction.
Zhang does not teach forming a contact structure having a lower resistance than the channel layer, Nor the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain.
Harari teaches a contact structure (754 and/or 755 fig. 7d-1) having a lower resistance than a channel layer (comprising 756 and 757 fig. 7d-1) [Sufficiently disclosed paragraph 0130, wherein contact structures 754 and 755 are disclosed as heavily doped polysilicon in “N+ doped polysilicon” and channel layer 756 and 757 are disclosed as lightly doped polysilicon “P- doped polysilicon”], the contact structure is interposed between the channel layer and at least a portion of a source and/or a drain [sufficiently illustrated fig. 7d-1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “a contact structure having a lower resistance than the channel layer, and the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain”.
A person of ordinary skill in the art would have been motivated to make this modification to reduce undesirable thermal diffusion of the dopants from the source/drains into the channel [sufficiently disclosed paragraph 0130 Harari “Because of the relatively significantly higher conductivity of the metallic material at the core, the N-type doping concentration of the ultra-thin N+ doped polysilicon can be reduced by one or two orders of magnitude, reducing undesirable thermal diffusion of the N-type dopant into the P-type dopant of the channel”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining known methods of manufacturing Three-dimensional vertical transistor structures with lateral channels for the purposes of forming memory and/or storage device.
Claim 2 Zhang in view of Harari teaches the method of claim 1, wherein forming the contact structure comprises:
forming a first contact structure wrapping around the drain [met in view of the modification in view of Harari as shown above, Harari 755 and/or 754 fig. 7d-1]; and
forming a second contact structure wrapping around the source [met in view of the modification in view of Harari as shown above, Harari 755 and/or 754 fig. 7d-1].
Claim 6 Zhang in view of Harari teach as shown above the method of claim 2, wherein the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure [disclosed with sufficient specificity Paragraph 0130 Harari “each of thickness between 5 and 15 nanometers” and/or they each have a width in the same range of 5-15 under broadest reasonable interpretation].
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the contact structure widths and the result effected variable thermal diffusion and/or buffer for thermal diffusion provided between the source/drain and the channel layer [sufficiently disclosed paragraph 0130 Harari].
Claim 7 Zhang in view of Harari teach as shown above the method of claim 2, wherein the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure [disclosed with sufficient specificity Harari Paragraph 0130 “each of thickness between 5 and 15 nanometers” an embodiment wherein the widths are different such as 5 nanometers and 15 nanometers at the extreme ends of the range].
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the contact structure widths and the result effected variable thermal diffusion and/or buffer for thermal diffusion provided between the source/drain and the channel layer [sufficiently disclosed paragraph 0130 Harari].
Claim 8 Zhang in view of Harari teach as shown above the method of claim 1, further comprising:
forming a stack (comprising 52 and 46 fig. 23A-24C) disposed on a radially outer surface of the memory layer in the second direction [sufficiently illustrated fig. 23A-23B], the stack comprising a plurality of insulating layers and the plurality of gate layers alternatively stacked on top each other [sufficiently illustrated fig. 23A-23 the plurality of insulating layer and plurality of gate layers alternatively stack on top each corresponding to a plurality of memory layers (sets of “memory layer – insulating layer – gate layer- insulating layer – memory layer” wherein insulating layer – gate layer – insulating layer” is an alternating stack), met under broadest reasonable interpretation].
Claim 10 Zhang teaches as shown above the method of claim 9,
Zhang does not teach forming a contact structure.
Harari teaches forming a contact structure (754 and 755 fig. 7D-1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that the method includes “forming a contact structure”.
A person of ordinary skill in the art would have been motivated to make this modification to reduce undesirable thermal diffusion of the dopants from the source/drains into the channel [sufficiently disclosed paragraph 0130 Harari “Because of the relatively significantly higher conductivity of the metallic material at the core, the N-type doping concentration of the ultra-thin N+ doped polysilicon can be reduced by one or two orders of magnitude, reducing undesirable thermal diffusion of the N-type dopant into the P-type dopant of the channel”].
Claim 11 Zhang in view of Harari teaches as shown above the method of claim 10, wherein the contact structure has a lower resistance than the channel layer [met in view of Harari sufficiently disclosed paragraph 0130, wherein contact structures 754 and 755 are disclosed as heavily doped polysilicon in “N+ doped polysilicon” and channel layer 756 and 757 are disclosed as lightly doped polysilicon “P- doped polysilicon”].
Claim 12 Zhang in view of Harari teaches as shown above the method of claim 11, wherein the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain [necessarily met in view of Harari as shown above to enable reduced thermal diffusion of dopants from the source/drain to the channel, sufficiently illustrated Harari fig. 7d-1].
Claim 13 Zhang in view of Harari teaches as shown above the method of claim 11, wherein forming the contact structure comprises:
forming a first contact structure wrapping around the drain [met in view of Harari sufficiently illustrated Harari fig. 7d-1, to enable reduced thermal diffusion of dopants from the source/drain to the channel]; and
forming a second contact structure wrapping around the source [met in view of Harari sufficiently illustrated Harari fig. 7d-1, to enable reduced thermal diffusion of dopants from the source/drain to the channel].
Claim 16 Zhang in view of Harari teaches as shown above the method of claim 13, wherein the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure [disclosed with sufficient specificity Paragraph 0130 Harari “each of thickness between 5 and 15 nanometers” and/or they each have a width in the same range of 5-15 under broadest reasonable interpretation].
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the contact structure widths and the result effected variable thermal diffusion and/or buffer for thermal diffusion provided between the source/drain and the channel layer [sufficiently disclosed paragraph 0130 Harari].
Claim 17 Zhang in view of Harari and Lue teaches as shown above the method of claim 13, wherein the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure [disclosed with sufficient specificity Harari Paragraph 0130 “each of thickness between 5 and 15 nanometers” an embodiment wherein the widths are different such as 5 nanometers and 15 nanometers at the extreme ends of the range].
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the contact structure widths and the result effected variable thermal diffusion and/or buffer for thermal diffusion provided between the source/drain and the channel layer [sufficiently disclosed paragraph 0130 Harari].
Claim 19 Zhang teaches as shown above the method of claim 18.
Zhang does not teach forming a contact structure having a lower resistance than the channel layer, wherein the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain.
Harari teaches a contact structure (754 and/or 755 fig. 7d-1) having a lower resistance than a channel layer (comprising 756 and 757 fig. 7d-1) [Sufficiently disclosed paragraph 0130, wherein contact structures 754 and 755 are disclosed as heavily doped polysilicon in “N+ doped polysilicon” and channel layer 756 and 757 are disclosed as lightly doped polysilicon “P- doped polysilicon”], the contact structure is interposed between the channel layer and at least a portion of a source and/or a drain [sufficiently illustrated fig. 7d-1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari such that “a contact structure having a lower resistance than the channel layer, wherein the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain”.
A person of ordinary skill in the art would have been motivated to make this modification to reduce undesirable thermal diffusion of the dopants from the source/drains into the channel [sufficiently disclosed paragraph 0130 Harari “Because of the relatively significantly higher conductivity of the metallic material at the core, the N-type doping concentration of the ultra-thin N+ doped polysilicon can be reduced by one or two orders of magnitude, reducing undesirable thermal diffusion of the N-type dopant into the P-type dopant of the channel”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining known methods of manufacturing Three-dimensional vertical transistor structures with lateral channels for the purposes of forming memory and/or storage device
Claims 3-5, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Harari as applied to the claims above, and further in view of US 11133329 B2 Lue et al hereafter “Lue”.
Claim 3 Zhang in view of Harari does teaches the method of claim 2, further comprising:
Forming a dielectric core (66 fig. 11A-11C )extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer [sufficiently illustrated fig. 11A-11C].
Zhang in view of Harari does not teach forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer,
wherein a portion the first contact structure is interposed between the gate extension structure and the drain.
Lue teaches forming gate extension structures (208 fig. 2, met under MPEP 2112.01 as the structures are structurally and/or compositionally the same) extending along portions of a channel layer (206 fig. 2) in the first direction (left to right of fig. 2), coupled to a radially inner surface of the channel layer [sufficiently illustrated fig. 2], interfacing outer surfaces of a source (210 fig. 2), a drain (212 fig. 2), and a dielectric core (214 fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari in further view of Lue such that the process includes “forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional separation between sources and/or drain [Lue column 6 lines 59 to column 7 line 5 in “As illustrated, the first conductive pillar 210 and the second conductive pillar 212 are separated from one another by both the insulator 214 and the insulating layer 208”] and/or to increase the effective channel length between source and drain structures [sufficiently illustrated fig. 2 Lue and in view of the disclosed separation of the source and drain column 6 lines 59 to column 7 line 5 ].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods of manufacturing vertical transistors with lateral channels for the purpose of forming memory and/or storage devices.
Claim 4 Zhang in view of Harari and Lue teaches as shown above the method of claim 3,
As rejected above Zhang in view Harari and Lue does not teach wherein the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width.
However, Lue does teach an embodiment (fig. 10) of the device as matched above and illustrated fig. 2 wherein the drain [see annotation below] has a drain first width [see annotation below] in the second direction at locations proximate to the gate extension structure [the side of the drain near the gate extension illustrated fig. 10], and a drain second width [see annotation below] in the second direction at locations distal from the gate extension structure [the side of the drain away from the gate extension structure illustrated fig. 10], the drain second width being larger than the drain first width [sufficiently illustrated fig. 10].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in further view of Lue such that “the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width”.
A person of ordinary skill in the art would have been motivated to modify the relative shape/widths of the drain and the gate extension structure to optimize the result effected variable of the separation between the source and drain structures along the channel and/or the effective channel length [sufficiently illustrated fig. 10 Lue and in view of the disclosed separation of the source and drain column 6 lines 59 to column 7 line 5].
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Annotated fig. 10: highlighting widths of a drain
Claim 5 Zhang in view of Harari and Lue teach as shown above the method of claim 3, wherein a first axial end of the gate extension structure is disposed axially outwards of an axially inward edge of the first contact structure that is proximate to the source in the first direction [met in view the modifications of Lue and Harari, wherein Lue teaches and sufficiently illustrates fig. 2 ~ the gate extension structure is disposed axially outwards of an axially inward edge of the source in the first direction~ and Harari teaches and illustrates fig. 7D-1 ~the first contact structure completely encloses the source and/or drain~], and a second axial end of the gate extension structure opposite the first axial end is axially aligned with the axially inward edge of the first contact structure [met in view of the modifications of Harari and Lue as discussed above wherein Harari illustrates fig. 2 a left and right end (first and second ends) of the gate extension structure are laterally aligned and/or aligned right to left (an axial direction) of fig. 2, in view of the modification of the first contact structure, the first contact structure is also aligned in this manner].
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Annotated fig. 16 Zhang: highlighting the direction of axial alignment for the source and drain
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Annotated fig. 7d-1 Harari: highlighting the direction of axial alignment of the contact structures.
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Annotated fig. 2 Lue: highlighting a direction of axial alignment across ends of the gate extension structure
Claim 14 Zhang in view of Harari teaches the method of claim 13, further comprising;
Forming a dielectric core (66 fig. 11A-11C)
Zhang in view of Harari does not teach forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer,
wherein a portion the first contact structure is interposed between the gate extension structure and the drain.
Lue teaches forming gate extension structures (208 fig. 2, met under MPEP 2112.01 as the structures are structurally and/or compositionally the same) extending along portions of a channel layer (206 fig. 2) in the first direction (left to right of fig. 2), coupled to a radially inner surface of the channel layer [sufficiently illustrated fig. 2], interfacing outer surfaces of a source (210 fig. 2), a drain (212 fig. 2), and a dielectric core (214 fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari in further view of Lue such that the process includes “forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional separation between sources and/or drain [Lue column 6 lines 59 to column 7 line 5 in “As illustrated, the first conductive pillar 210 and the second conductive pillar 212 are separated from one another by both the insulator 214 and the insulating layer 208”] and/or to increase the effective channel length between source and drain structures [sufficiently illustrated fig. 2 Lue and in view of the disclosed separation of the source and drain column 6 lines 59 to column 7 line 5 ].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods of manufacturing vertical transistors with lateral channels for the purpose of forming memory and/or storage devices.
Claim 15 Zhang in view of Harari and Lue as shown above the method of claim 14,
As rejected above Zhang in view Harari and Lue does not teach wherein the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width.
However, Lue does teach an embodiment (fig. 10) of the device as matched above and illustrated fig. 2 wherein the drain [see annotation below] has a drain first width [see annotation below] in the second direction at locations proximate to the gate extension structure [the side of the drain near the gate extension illustrated fig. 10], and a drain second width [see annotation below] in the second direction at locations distal from the gate extension structure [the side of the drain away from the gate extension structure illustrated fig. 10], the drain second width being larger than the drain first width [sufficiently illustrated fig. 10].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in further view of Lue such that “the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width”.
A person of ordinary skill in the art would have been motivated to modify the relative shape/widths of the drain and the gate extension structure to optimize the result effected variable of the separation between the source and drain structures along the channel and/or the effective channel length [sufficiently illustrated fig. 10 Lue and in view of the disclosed separation of the source and drain column 6 lines 59 to column 7 line 5].
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Annotated fig. 10: highlighting widths of a drain
Claim 20 Zhang in view of Harari teaches as shown above the method of claim 19, further comprising a dielectric core (66 fig. 10A-10C).
Zhang in view of Harari does not teach forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer, wherein a portion the first contact structure is interposed between the gate extension structure and the drain.
Lue teaches forming gate extension structures (208 fig. 2, met under MPEP 2112.01 as the structures are structurally and/or compositionally the same) extending along portions of a channel layer (206 fig. 2) in the first direction (left to right of fig. 2), coupled to a radially inner surface of the channel layer [sufficiently illustrated fig. 2], interfacing outer surfaces of a source (210 fig. 2), a drain (212 fig. 2), and a dielectric core (214 fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang in view of Harari in further view of Lue such that the process includes “forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer”.
A person of ordinary skill in the art would have been motivated to make this modification to provide additional separation between sources and/or drain [Lue column 6 lines 59 to column 7 line 5 in “As illustrated, the first conductive pillar 210 and the second conductive pillar 212 are separated from one another by both the insulator 214 and the insulating layer 208”] and/or to increase the effective channel length between source and drain structures [sufficiently illustrated fig. 2 Lue and in view of the disclosed separation of the source and drain column 6 lines 59 to column 7 line 5 ].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods of manufacturing vertical transistors with lateral channels for the purpose of forming memory and/or storage devices.
Conclusion
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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