DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant’s election without traverse is acknowledged. The Examiner agrees with the amended claim groupings and therefore an action on the merits of claim 1-17 and 21-23 follows.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,376,504. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the later clearly dominate the claims of the instant application. Furthermore, the instant claims nominally are recited as a “method of forming” without any specific step/order to the formation of the elements. Since the ‘504 contains all the formed elements, it inherently teaches the generic method of forming such elements.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recties on line 3 “forming a phase change memory element” and then later on line 5 “forming a phase change memory element” which is thought to be a duplication error.
Claim 12 recties on line 4 “a second side of the wafer” for which there is no antecedent first side nor wafer.
Claim 12 recties on line 6 “forming the phase change memory element” as a step “after bonding” in the preamble and after the previous forming of the phase change memory.
Claim 13 recites on line 3 “the second metal contact” for which there is no antecedent basis.
The respective dependent claims inherit the deficiencies of their parents outlined above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2021/0296396) in view of Huggins (US 2004/0001368).
Regarding claim 1, Wu discloses a method, comprising: forming a transistor (see paragraph 0045) in a first chip (see Figure 5); forming a phase change memory element (60, paragraph 0023) in the first chip electrically coupled to the transistor, the transistor and the phase change memory element being a memory cell (see abstract).
Wu fails to teach bonding a second chip to the first chip wherein the transistor is positioned between the phase change memory element and the second chip. However, this describes the “first” chip of Wu bonded on a second chip from the bottom in Figure 5 and viewed from the bottom (i.e. inverted).
Huggins teaches a memory device on a first chip that is inverted and bonded to a second chip (see Figures 42-46). Therefore, it would have been obvious to one having ordinary skill at the time of filing to bond a second chip to the first chips as shown by Huggins in order to allow for handling while forming structures on the backside of the first chip (see Huggins Figure 50 for example).
Regarding claim 2, Wu as modified above discloses the method of claim 1, comprising forming a first electrode (63) of the memory cell coupled between the phase change memory element and the transistor.
Regarding claim 3, Wu discloses the method of claim 2, comprising forming a second electrode (68) of the memory cell coupled to the phase change memory element, the phase change memory element positioned between the first electrode and the second electrode.
Regarding claim 4, Wu discloses the method of claim 3, wherein the first chip further includes: a first metal line (56B) coupled to the second electrode and positioned on a first side of the first chip distal to the second chip; but fails to teach a second metal line coupled to the gate electrode and positioned on a second side of the first chip proximal to the second chip. However, one of ordinary skill would realize the need for a control line to connect to the gate and control the gate voltage. The positioning of the lines relative to the chips is merely the optimization of a layout and there being on two options (proximate and distant) it would have been further obvious to try both configurations to achieve the optimal layout of the lines.
Regarding claim 5, Wu discloses the device of claim 4, wherein the first metal line is one of a first bitline or a first wordline coupled to the memory cell, and wherein the second metal line is either a second wordline or a second bitline coupled to the memory cell (these are mere names and impart no structure to the device).
Regarding claim 8, Wu discloses the method of claim 2, wherein the phase change material includes GeSbTe (See paragraph 0023).
Regarding claim 9, Wu discloses the method of claim 2, While Wu does not explicitly disclose that the phase change element stores data, it would have been further obvious to one having ordinary skill to use the phase change element to store data since this is common and well known in the art to use the phase change to represent different data states.
Regarding claim 10, Wu discloses the method of claim 2 but fails to teach the first electrode is a heater element configured to heat the phase change memory element to write or erase data from the phase change element. However, the use of such heaters to aid in the program/erase of phase change memories are common and well-known in the art. Further, the placement of such a heater near the phase change element would be obvious to reduce power consumption.
Regarding claim 11, Wu as modified above discloses the a method, comprising forming a transistor (see paragraph 0045) in a first wafer (Figure 5); forming a first metal line (56B bottom or 56A) coupled to the transistor in the first wafer; bonding the first wafer to a second wafer (in view of the modification above with Huggins); forming, in the first wafer, a phase change memory element ( 60) coupled to the transistor, the transistor positioned between the phase change memory element and the second wafer (see rejection of claim 1 above), wherein the transistor and the phase change memory element are a memory cell; and forming, in the first wafer, a second metal line (56B top or 63) coupled to the phase change memory element.
Claim(s) 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2021/0296396), Huggins (US 2004/0001368) as presented above and further in view of Hasnat (US 2019/0043868).
Regarding claim 12, inasmuch as understood, Wu as modified above discloses the method of claim 11, but fails to teach after bonding the first wafer to the second wafer: exposing a source or drain terminal of the transistor by removing a semiconductor layer from a second side of the wafer; forming a first electrode in contact with the exposed source or drain terminal; and forming the phase change memory element in contact with the first electrode. However, this technicque of backside fabrication was well known at the time of filing. For example, Hasnat teaches the removal of a substrate (wafer) layer after the bonding step to expose connection lines (e.g. Figure 4C-4E, 427) for connection to backside structure. Therefore, it would have been obvious to one having ordinary skill at the time of filing to expose a source or drain terminal (10 when flipped) of the transistor by removing a semiconductor layer (11 when flipped) from a second side of the wafer; forming a first electrode (413 Figure 4E of Hasnat) in contact with the exposed source or drain terminal; and forming the phase change memory element in contact with the first electrode (phase change is in contact with the S/D via the transistor).
Regarding claim 13, Wu discloses the method of claim 12, further comprising: forming a second electrode in contact with the phase change memory element; and forming the second metal interconnect in contact with the second electrode (inasumuch as understood, the combine teachigns comprise multiple levels and layers of interconnects which one of ordinary skill would find necessary and obvious for communication to/from the memory).
Regarding claim 14, Wu discloses the method of claim 12, but fails to teach the first wafer is silicon-on-insulator wafer, wherein removing the semiconductor layer includes removing a bulk semiconductor layer of the silicon-on-insulator wafer. However, it would have been obvious to one having ordinary skill at the time of filing to implement this combined device as SOI since such SOI architecture was well-known at the time of filing as are its benefits (e.g. thermal isolation). The bulk layer being on the “bottom” when flipped would be removed as taught by Hasnat.
Regarding claim 15, Wu discloses the method of claim 14, wherein exposing the source or drain terminal includes removing an oxide layer of the silicon-on-insulator wafer (in the combined device, the oxide layer would need to be removed to access the circuitry).
Regarding claim 16, Wu discloses the method of claim 11, further comprising forming an integrated circuit including the memory cell by dicing the first and second wafers (see Hasnat paragraph 0020).
Regarding claim 17, Wu discloses the method of claim 16, wherein the integrated circuit includes: a first chip diced from the first wafer and including the memory cell; and a second chip diced from the second wafer (this is what the combined device would be after the claim 16 dicing).
Claim(s) 6, 7 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2021/0296396) and Huggins (US 2004/0001368) and further in view of Cheng (US 2019/0157420).
Regarding claim 21, Wu discloses a method, comprising: forming, in a first chip memory cell including a transistor (in 51) and phase change memory cell (in 61), wherein forming each memory cell includes: forming, in a first chip, a plurality of stacked channels (52) of a transistor ; forming a gate electrode (54) forming a source terminal in contact with the channels (10); forming a drain terminal in contact with channel (56B)s; and forming a phase change memory element coupled to the either the source terminal or the drain terminal; and bonding a second chip to the first chip (see rejection of claim 1 above).
Wu fails to specifically teach a plurality of the memory cells in an array and that the gates wrapped around the channels (i.e. gate all around).
However, such transistors were known in the art at the time of filing. For example, Cheng discloses a transistor of similar structure with an all around gate stack (see Figure 14) comprising a metal gate (50) surrounding the nanosheets (21) and dielectric (48). Therefore, it would have been obvious to one having ordinary skill at the time of filing implement the gate surround as taught by Cheng since this was a known technique at the time of filing, yields the predictable result of a functional gate and since such all around gates are known to have well known benefits such as reduced leakage current. Furthermore, it would have been obvious at the time of filing to provide for plurality of such cells in an array in order to provide for larger amounts of data storing in a conventional access of an array.
Regarding claim 22, Wu discloses the method of claim 21, wherein each memory cell further comprises an electrode (63) in contact with the source or drain terminal and the phase change memory element.
Regarding claim 23, Wu discloses the method of claim 22, wherein the electrode is positioned between the source or drain terminal and the phase change memory element (63 between 65 and 56B).
Regarding claim 6, Wu discloses the method of claim 2, wherein the transistor is a gate all around transistor including: a plurality of semiconductor nanosheets; a gate dielectric surrounding the semiconductor nanosheets; a gate electrode including a gate metal surrounding the semiconductor nanosheets and separated from the semiconductor nanosheets by the gate dielectric; a source terminal coupled to the semiconductor nanosheets; and a drain terminal coupled to the semiconductor nanosheets (see rejection of claim 21 above).
Regarding claim 7, Wu discloses the method of claim 6, wherein the first electrode is in contact with either the source terminal or the drain terminal (see rejection of claim 22 above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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