DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 7-9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizu (PGPUB 20190355397), hereinafter as Ishizu.
Regarding claim 1, Ishizu teaches a memory circuit, comprising: a memory array comprising a plurality of memory cells (Fig 1);
a first pre-charge circuit (Fig 3, circuit 51) coupled to at least one access line (Fig 3, LRBL) electrically connected to the plurality of memory cells, and configured to be in a first state during a standby mode (claim 23) of the memory array; and
a second pre-charge circuit (Fig 3, circuit 52) coupled to the at least one access line, and configured to be in a second state during the standby mode (claim 23, “standby state…the first precharge voltage is applied to the bit line pair by the first precharge circuit, the second precharge circuit is off”).
Regarding claim 2, Ishizu teaches the second state is indicative of an inactive pre-charge circuit to suspend charging the at least one access line (claim 23, second precharger is off)
and the first state is indicative of an active pre-charge circuit to charge the at least one access line to a supply voltage (claim 23, first precharger is on),
and wherein in the first state during the standby mode, the first pre-charge circuit is configured to charge the at least one access line to the supply voltage prior to accessing the plurality of memory cells (claim 23).
Regarding claim 3, Ishizu teaches the standby mode is associated with a time period when an access operation is suspended (claim 23, standby).
Regarding claim 4, Ishizu teaches the first pre-charge circuit is configured to be in the second state to suspend charging the at least one access line during a read operation and a write operation of the plurality of memory cells (claim 23) ; and the second pre-charge circuit remains in the second state during the read operation and the write operation (claim 23 “for a shift from the first state to the second state, the first precharge circuit and the first and second switch circuits are turned off ”).
Regarding claim 5, Ishizu teaches the read operation and the write operation of the plurality of memory cells correspond to an access operation performed in one clock cycle (Fig 17, Q1 node within one CK cycle).
Regarding claim 11, Ishizu teaches the at least one access line comprises a first access line and a second access line;
the first pre-charge circuit comprises: a first transistor operatively coupled to the first access line, a second transistor operatively coupled to the second access line, and a third transistor operatively coupled to the first access line and the second access line, and configured to equalize charges of the first access line and the second access line, wherein respective gates of the first, second, and third transistors are operatively coupled (Fig 3 precharge circuit 51 has three transistors doing functions, and has gates coupled together); and
the second pre-charge circuit comprises: a fourth transistor operatively coupled to the first access line, a fifth transistor operatively coupled to the second access line, and a sixth transistor operatively coupled to the first access line and the second access line, and configured to equalize charges of the first access line and the second access line, wherein respective gates of the fourth, fifth, and sixth transistors are operatively coupled (Fig 3 precharge circuit 52 has three transistors doing functions, and has gates coupled together).
Regarding claim 12, Ishizu teaches a memory circuit, comprising:
a memory array comprising a plurality of memory cells (Fig 1/3);
a pre-charge circuit (Fig 3, 51) coupled to a first access line and a second access line (Fig 3, LRBL and LRBLB) electrically connected to the plurality of memory cells, and configured to be in a low state during a standby mode of the memory array (claim 23); and
an equalizer circuit (Fig 3, circuit 52) coupled to the first access line and the second access line, and configured to be in a high state during the standby mode (claim 23).
Regarding claim 13, Ishizu teaches the high state is indicative of an inactive pre-charge circuit to suspend charging the first access line and the second access line or an inactive equalizer circuit to suspend equalizing charges of the first access line and the second access line (claim 23), and the low state is indicative of an active pre-charge circuit to charge the first access line and the second access line to a supply voltage or an active equalizer circuit to equalize charges of the first access line and the second access line (claim 23), and wherein in the low state during the standby mode, the pre-charge circuit is configured to charge the first access line and the second access line to the supply voltage prior to accessing the plurality of memory cells (claim 23).
Regarding claim 14, Ishizu teaches the pre-charge circuit is configured to be in the high state to suspend charging at least one of the first access line or the second access line during a read operation and a write operation of the plurality of memory cells (claim 23); the equalizer circuit remains in the high state during the read operation and the write operation to suspend equalizing a first charge of the first access line to a second charge of the second access line (claim 23); and the pre-charge circuit and the equalizer circuit are in the low state between the read operation and the write operation, wherein in the low state, the pre-charge circuit is configured to charge the first access line and the second access line to a supply voltage and the equalizer circuit is configured to equalize the first charge of the first access line to the second charge of the second access line (claim 23).
Regarding claim 15, argument used in rejection of claim 5 applies.
Regarding claim 16, Ishizu teaches a respective time period of at least one of the read operation, the write operation, the high state of the pre-charge circuit, the low state of the pre-charge circuit and the equalizer circuit between the read operation and the write operation, or between the read operation and the write operation is predefined (claim 23, during standby period, high in precharge state and low in equalizer state).
Regarding claim 17, Ishizu teaches the pre-charge circuit comprises: a first transistor operatively coupled to the first access line, a second transistor operatively coupled to the second access line, and a third transistor operatively coupled to the first access line and the second access line, and configured to equalize the first access line and the second access line, wherein respective gates of the first, second, and third transistors are operatively coupled (Fig 3, transistors of precharger 51); and
the equalizer circuit comprises: a fourth transistor (Fig 3, within 52, a transistor with S/D connected to a pair of BLs) operatively coupled to the first access line and the second access line, and configured to equalize charges of the first access line and the second access line.
Regarding claim 18, Ishizu teaches a method, comprising:
activating a first pre-charge circuit, coupled to at least one access line electrically connected to a plurality of memory cells of a memory array, during a standby mode of the memory array, wherein activating the first pre-charge circuit charges the at least one access line to a supply voltage (Fig 3, precharger 51, and claim 23); and
deactivating a second pre-charge circuit, coupled to the at least one access line, during the standby mode of the memory array, wherein deactivating the second pre-charge circuit suspends charging the at least one access line (Fig 3, precharger 52, and claim 23).
Regarding claim 19, Ishizu teaches
deactivating the first pre-charge circuit during a read operation or a write operation of the memory array (claim 23); and
deactivating the second pre-charge circuit during the read operation or the write operation of the memory array (claim 23).
Regarding claim 20, Ishizu teaches
activating the first pre-charge circuit and the second pre-charge circuit during the standby mode of the memory array associated with a time period between a read operation and a write operation (claim 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizu.
Regarding claim 10, Ishizu teaches one or more of the plurality of memory cells correspond to a pseudo-dual-port (PDP) static random access memory (SRAM), wherein the PDP SRAM is configured to performing a read operation and a write operation within one clock cycle ([0049] “SRAM”, the examiner takes note it is well known PDP SRAM can be used as a SRAM).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizu, over Ikeda (Patent 10643689), hereinafter as Ikeda.
Regarding claim 6, Ishizu teaches a circuit as in rejection of claim 4,
But not expressly the first pre-charge circuit and the second pre-charge circuit are in the first state during a predefined time period between the read operation and the write operation to charge the at least one access line;
Ikeda teaches the first pre-charge circuit and the second pre-charge circuit are in the first state during a predefined time period between the read operation and the write operation to charge the at least one access line (col 7 line 5-15).
Since Ikeda and Ishizu are both from the same field of semiconductor memory device, the purpose disclosed by Ikeda would have been recognized in the pertinent art of Ishizu.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use predetermined precharging time as in Ikeda into the device of Ishizu for the purpose of managing read/write operation of the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827