Prosecution Insights
Last updated: October 22, 2026
Application No. 18/786,469

Electroless Plating Method for Metal Gate Fill

Non-Final OA §DOUBLEPATENT
Filed
Jul 27, 2024
Priority
Sep 22, 2020 — provisional 63/081,397 +2 more
Examiner
KIM, TONG-HO
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1045 granted / 1097 resolved
+35.3% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
47 currently pending
Career history
1149
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.5%
+5.5% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/27/2024, 1/21/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claim 3 is objected to because of the following informalities: In claim 3, line 2, the limitation of “that” should be corrected into “than”. Appropriate correction is required. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 2-7, 9-11 and 13-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 9-10, 13, 15, 17 and 20 of U.S. Patent No. 12,107,150 in view of Bergendahl (US 2017/0222024). Regarding claim 2, Pat '150 discloses, in claim 1, a method comprising: plating a metal into the recess using an aqueous plating solution, the metal filling up the recess, the aqueous plating solution comprising suppressors, wherein the suppressors are more densely distributed at sidewalls of the recess than at a bottom of the recess during plating the metal ("providing an aqueous plating solution to the first opening to plate a metal into the first opening, the metal filling up the first opening, the aqueous plating solution comprising suppressors, wherein the suppressors are more densely distributed at sidewalls of the first opening than at a bottom of the first opening during plating the metal", in claim 1 of Pat '150, is interpreted as the same limitation). Pat '150 does not explicitly disclose forming a recess in one or more material layers. Bergendahl teaches, in at least figures 19, 23, and related text, the method comprising forming a recess (2101, [75]) in one or more material layers (1302/1902, [60], [69]), for the purpose of providing formation of replacement metal gate stacks ([78]). Pat '150 and Bergendahl are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '150 with the specified features of Bergendahl because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '150 to have the forming a recess in one or more material layers, as taught by Bergendahl, for the purpose of providing formation of replacement metal gate stacks ([78], Bergendahl). Regarding claim 3, Pat '150 in view of Bergendahl discloses the method of claim 2 as described above. Pat '150 in view of Bergendahl does not explicitly disclose the plating plates a bottom of the recess at a higher rate that a sidewall of the recess. Pat '150 teaches, in claim 9, the plating plates a bottom of the recess at a higher rate that a sidewall of the recess ("chemically plating a conductive fill in the opening, at a plating rate which is 10 to 25 times greater at a bottom of the opening than at sides of the opening", in claim 9 of Pat '150, is interpreted as the same limitation), for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claim 1 of Pat '150 in view of Bergendahl to have the plating plating a bottom of the recess at a higher rate that a sidewall of the recess, as taught by claim 9 of Pat '150, for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Regarding claim 4, Pat '150 in view of Bergendahl discloses the method of claim 2 as described above. Pat '150 further discloses, in claim 2, the aqueous plating solution further comprises a reducer ("the aqueous plating solution further comprises metal ions or metal salts, a reducer, and accelerators", in claim 2 of Pat '150, is interpreted as the same limitation). Regarding claim 5, Pat '150 in view of Bergendahl discloses the method of claim 2 as described above. Pat '150 further discloses, in claim 2, the aqueous plating solution further comprises accelerators ("the aqueous plating solution further comprises metal ions or metal salts, a reducer, and accelerators", in claim 2 of Pat '150, is interpreted as the same limitation). Regarding claim 6, Pat '150 in view of Bergendahl discloses the method of claim 5 as described above. Pat '150 further discloses, in claim 3, the aqueous plating solution further comprises accelerators ("the accelerators are more densely distributed at the bottom of the first opening than at the sidewalls of the first opening during plating the metal", in claim 3 of Pat '150, is interpreted as the same limitation). Regarding claim 7, Pat '150 in view of Bergendahl discloses the method of claim 5 as described above. Pat '150 in view of Bergendahl does not explicitly disclose an overall ratio of accelerators to suppressors by weight in the plating solution is between 1:5 and 5:1. Pat '150 teaches, in claim 13, an overall ratio of accelerators to suppressors by weight in the plating solution is between 1:5 and 5:1 (all limitations are the same with the limitations recited in claim 13 of Pat '150), for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claim 1 of Pat '150 in view of Bergendahl to have the overall ratio of accelerators to suppressors by weight in the plating solution being between 1:5 and 5:1, as taught by claim 13 of Pat '150, for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Regarding claim 9, Pat '150 discloses, in claims 15 and 20, a method comprising: the opening having a height-to-width ratio between 10:1 and 20:1 in a cross-sectional view; and placing the substrate with the one or more material layers into a chemical bath to plate a metal fill in the opening, the chemical bath including suppressors and accelerators, wherein a ratio of accelerators to suppressors at a bottom of the opening may be between 10:1 to 100:1 ("removing a dummy gate to form a recess exposing a nanostructure channel region, wherein a height to width ratio of the recess is between 10:1 and 20:1; depositing the gate electrode comprises: providing a plating solution into the recess, the plating solution including chemical accelerators and chemical suppressors, and reducing a metal from the plating solution to deposit the metal in the recess" and “while providing the plating solution into the recess, a ratio of the chemical accelerators to the chemical suppressors is between 10:1 and 100:1 at a bottom of the recess”, in claims 15 and 20 of Pat '150, are interpreted as the same limitation). Pat '150 does not explicitly disclose forming an opening in one or more material layers over a substrate. Bergendahl teaches, in at least figures 19, 23, and related text, the method comprising forming an opening (2101, [75]) in one or more material layers (1302/1902, [60], [69]) over a substrate (102, [40]), for the purpose of providing formation of replacement metal gate stacks ([78]). Pat '150 and Bergendahl are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '150 with the specified features of Bergendahl because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '150 to have the forming an opening in one or more material layers over a substrate, as taught by Bergendahl, for the purpose of providing formation of replacement metal gate stacks ([78], Bergendahl). Regarding claim 10, Pat '150 in view of Bergendahl discloses the method of claim 9 as described above. Pat '150 further discloses, in claim 15, the metal fill is a gate electrode ("depositing the gate electrode comprises: providing a plating solution into the recess, the plating solution including chemical accelerators and chemical suppressors, and reducing a metal from the plating solution to deposit the metal in the recess", in claim 15 of Pat '150, is interpreted as the same limitation). Regarding claim 11, Pat '150 in view of Bergendahl discloses the method of claim 9 as described above. Pat '150 in view of Bergendahl does not explicitly disclose the metal fill is plated at a plating rate that is 10 to 25 times greater at a bottom of the opening than at sides of the opening. Pat '150 teaches, in claims 9 and 10, the metal fill is plated at a plating rate that is 10 to 25 times greater at a bottom of the opening than at sides of the opening ("chemically plating a conductive fill in the opening, at a plating rate which is 10 to 25 times greater at a bottom of the opening than at sides of the opening" and “the plating comprises: providing a plating solution to the opening, the plating solution comprising a metal ion and a reducing agent”, in claims 9 and 10 of Pat '150, are interpreted as the same limitation), for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 15 and 20 of Pat '150 in view of Bergendahl to have the metal fill is plated at a plating rate that is 10 to 25 times greater at a bottom of the opening than at sides of the opening, as taught by claims 9 and 10 of Pat '150, for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Regarding claim 13, Pat '150 in view of Bergendahl discloses the method of claim 9 as described above. Pat '150 in view of Bergendahl does not explicitly disclose the chemical bath further comprises a reducing agent. Pat '150 teaches, in claim 10, the chemical bath further comprises a reducing agent (“the plating comprises: providing a plating solution to the opening, the plating solution comprising a metal ion and a reducing agent”, in claim 10 of Pat '150, is interpreted as the same limitation), for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 15 and 20 of Pat '150 in view of Bergendahl to have the chemical bath further comprising a reducing agent, as taught by claims 9 and 10 of Pat '150, for the purpose of providing electro-chemical plating technique and accelerators and suppressors to achieve deposition of the gate electrode fill in a bottom up manner. Regarding claim 14, Pat '150 in view of Bergendahl discloses the method of claim 9 as described above. Pat '150 further discloses, in claim 17, the metal fill is free of fluorine ("the gate electrode is free of fluorine", in claim 17 of Pat '150, is interpreted as the same limitation). Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 13, 15 and 20 of U.S. Patent No. 12,107,150 in view of Bergendahl (US 2017/0222024), and further in view of Moon (US 2014/0084473). Regarding claim 8, Pat '150 in view of Bergendahl discloses the method of claim 7 as described above. Pat '150 in view of Bergendahl does not explicitly disclose the accelerators include bis(3- sulfopropyl)disulfide (SPS), wherein the suppressors include polyethylene glycol (PEG). Moon teaches, in at least figures 2-4 and related text, the method comprising the accelerators include bis(3- sulfopropyl)disulfide (SPS) ([86]), wherein the suppressors include polyethylene glycol (PEG) ([86]), for the purpose of providing a semiconductor package with through electrodes configured to reduce an extrusion of crystal grains therein ([5]). Pat '150, Bergendahl, and Moon are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '150 in view of Bergendahl with the specified features of Moon because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '150 in view of Bergendahl to have the accelerators including bis(3- sulfopropyl)disulfide (SPS), wherein the suppressors include polyethylene glycol (PEG), as taught by Moon, for the purpose of providing a semiconductor package with through electrodes configured to reduce an extrusion of crystal grains therein ([5], Moon). Regarding claim 15, Pat '150 in view of Bergendahl discloses the method of claim 9 as described above. Pat '150 in view of Bergendahl does not explicitly disclose the accelerators include bis(3- sulfopropyl)disulfide (SPS), wherein the suppressors include polyethylene glycol (PEG). Moon teaches, in at least figures 2-4 and related text, the method comprising the accelerators include bis(3- sulfopropyl)disulfide (SPS) ([86]), wherein the suppressors include polyethylene glycol (PEG) ([86]), for the purpose of providing a semiconductor package with through electrodes configured to reduce an extrusion of crystal grains therein ([5]). Pat '150, Bergendahl, and Moon are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '150 in view of Bergendahl with the specified features of Moon because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '150 in view of Bergendahl to have the accelerators including bis(3- sulfopropyl)disulfide (SPS), wherein the suppressors include polyethylene glycol (PEG), as taught by Moon, for the purpose of providing a semiconductor package with through electrodes configured to reduce an extrusion of crystal grains therein ([5], Moon). Allowable Subject Matter Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 9 and 12 that recite "a ratio of suppressors to the accelerators on a sidewall of the opening at a midpoint between a top of the opening and a bottom of the opening is in a range of 10:1 to 50:1" in combination with other elements of the base claims 9 and 12. Claims 16-21 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 16 that recite "a ratio of suppressors to the accelerators on a sidewall of the opening at a midpoint between a top of the opening and a bottom of the opening is in a range of 10:1 to 50:1" in combination with other elements of the base claims 16. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONG-HO KIM/ Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jul 27, 2024
Application Filed
Aug 13, 2024
Response after Non-Final Action
Oct 07, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.7%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allowance rate.

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