DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recited the limitation “through vias” in lines 2-3 is unclear, do through vias include the through via as claimed in claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2019/0131276).
As for claim 2, Chen et al. disclose in Fig. 3A-3H, 6 and the related text a semiconductor device, comprising:
a first die 100, wherein the first die comprises a semiconductor substrate 102, an interconnect structure 108 on a first (lower) side of the semiconductor substrate, and a first through via 115 extending from a first (lower) surface of the semiconductor substrate toward a second (upper) surface of the semiconductor substrate (Fig. 3H);
a first isolation structure (right portion of) 334a in a first recess (right 324a) in the second surface of the semiconductor substrate (Fig. 3H), wherein the first through via 115 extends through the first isolation structure, wherein a first surface of the first isolation structure is level with the second surface of the semiconductor substrate (Fig. 3H); and an encapsulant 118/22 along sidewalls of the first die (Fig. 3H/6).
As for claim 3, Chen et al. disclose the semiconductor device of claim 2, further comprising: a buffer layer 320a disposed over the first die, the first isolation structure, and the encapsulant (Fig. 3H).
As for claim 4, Chen et al. disclose the semiconductor device of claim 3, further comprising: a conductive terminal 228/328 disposed over the buffer layer, wherein the conductive terminal is electrically connected to the first through via (Fig. 3H).
As for claim 5, Chen et al. disclose the semiconductor device of claim 4, further comprising: a dummy terminal 212 over the buffer layer, wherein the first isolation structure extends below the dummy terminal (Fig. 3H).
As for claim 6, Chen et al. disclose the semiconductor device of claim 2, further comprising: a second die 200 bonded to the first die 100, wherein the interconnect structure 225 is between the second die and the semiconductor substrate (Fig. 3H).
As for claim 7, Chen et al. disclose the semiconductor device of claim 2, further comprising: a second isolation structure (left portion of 324a) in a second recess (left 324a) in the second surface of the semiconductor substrate, wherein (upper portion of) the second isolation structure is free of through vias (Fig. 3H).
As for claim 8, Chen et al. disclose the semiconductor device of claim 2, wherein the first isolation structure 334a comprises: a first insulating layer (lower portion of 334a that form in 324a) on the semiconductor substrate and along sidewalls of the first through via (Fig. 3H); and a second insulating layer (upper portion of 334 that does not form in 324a) on the first insulating layer (Fig. 3H), wherein a (upper) surface of the first insulating layer and a (lower) surface of the second insulating layer are level with a (upper) surface of the encapsulant 118 (Fig. 3H).
As for claim 9, Chen et al. disclose in Fig. 3A-3H, 6 and the related text a semiconductor device, comprising:
a first die 100, wherein the first die comprises a semiconductor substrate 102, the first die further comprising a first through via (right 115) and a second through via (left 115) extending through the semiconductor substrate, the semiconductor substrate having a first recess (right 324a);
a first isolation structure (right portion of 334a) in the first recess, the first isolation structure surrounding the first through via (Fig. 3H);
a first encapsulant 118 along sidewalls of the first die (Fig. 3H);
an insulating layer 320 over the first die, the first isolation structure, and the first encapsulation (Fig. 3H); and
a conductive terminal 228/328 over the insulating layer, wherein the conductive terminal is electrically connected to first through via (Fig. 3H).
As for claim 10, Chen et al. disclose the semiconductor device of claim 9, wherein the first isolation structure (right portion of 334a) surrounds the second through via (Fig. 3H).
As for claim 11, Chen et al. disclose the semiconductor device of claim 9, wherein the semiconductor substrate comprises a second recess (left 324a), further comprising: a second isolation structure (left portion of 334a) disposed in the second recess, wherein the second isolation structure surrounds the second through via (Fig. 3H).
As for claim 12, Chen et al. disclose the semiconductor device of claim 11, wherein (a portion of) a width of the first isolation structure is different than (a entire portion) a width of the second isolation structure (Fig. 3H).
As for claim 13, Chen et al. disclose the semiconductor device of claim 9, wherein the semiconductor substrate comprises a second recess (right 324), further comprising: a second isolation structure (left portion of 334a) disposed in the second recess, wherein the second isolation structure does not (directly) contact conductive material 108 of the first die (Fig. 3H).
As for claim 14, Chen et al. disclose the semiconductor device of claim 9, further comprising:a second die 200 bonded to the first die; and a second encapsulant (outer portion of 22) along sidewalls of the first encapsulant and along sidewalls of the second die (Fig. 6).
As for claim 15, Chen et al. disclose the semiconductor device of claim 14, further comprising:a redistribution structure 23 over the first die and the second encapsulant; and a third through via 14 extending through the second encapsulant (Fig. 6).
As for claim 16, Chen et al. disclose in Fig. 3A-3H, 6 and the related text a semiconductor device, comprising:
a first die 100 comprising a semiconductor substrate, an interconnect structure 108 on the semiconductor substrate 102, and a first through via (right) 115 in the semiconductor substrate;
a first substrate C/23 attached to the first die (Fig. 3H/6), wherein the interconnect structure is between the semiconductor substrate and the first substrate (Fig. 3H/6);
a first encapsulant 118/22 over the first substrate, wherein the first encapsulant extends along sidewalls of the first die (Fig. 3H/6); a first isolation structure (left) 334a on a surface of the semiconductor substrate; and
a buffer layer 320a over and contacting the first isolation structure, the first die, and the first encapsulant (fig. 3H), wherein a first (upper) surface of the first isolation structure is level with a first (upper) surface of the semiconductor substrate (Fig. 3H).
As for claim 17, Chen et al. disclose the semiconductor device of claim i6, wherein the first through via 15 extends into the first isolation structure (Fig. 3H).
As for claim 18, Chen et al. disclose the semiconductor device of claim i6, wherein the first die comprises one or more additional through vias 115 (Fig. 3H), the one or more additional through vias extending into the first isolation structure (Fig. 3H).
As for claim 19, Chen et al. disclose the semiconductor device of claim i6, wherein the first isolation structure comprises: a first isolation sub-layer (left portion of 334a that form in left 324a); and a second isolation sub-layer (right portion of 334a that form in right 324a) over the first isolation sub-layer, wherein the first isolation sub-layer (left portion of 334a that form in left 324a); separates the second isolation sub-layer from the first through via (Fig. 3H).
As for claim 20, Chen et al. disclose the semiconductor device of claim i6, further comprising: a second isolation structure (left 334a) on the surface of first semiconductor substrate, wherein the buffer layer 320a is over and contacts the second isolation structure (Fig. 3H), wherein a first surface of the second isolation structure is level with the first surface of the semiconductor substrate (Fig. 3H).
As for claim 21, Chen et al. disclose the semiconductor device of claim 20, wherein the first die comprises one or more additional through vias 115/328, wherein a first number of through vias 115 extend into the first isolation structure, wherein a second number of through vias 115/328 extend into the second isolation structure, wherein the first number is different than the second number (Fig. 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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