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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,381,181. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 1-20 of the present invention are recited within claims 1-20 of U.S. Patent No. 12,381,181.
Application No. 18/786,510
U.S. Patent No. 12,381,181 (reference)
Claim 1: A method of forming a semiconductor device, the method comprising: mounting a first semiconductor die on a substrate (“support substrate”); mounting a second semiconductor die on the substrate (“support substrate”), such that the first semiconductor die and the second semiconductor die are separated; depositing a first dielectric material layer between the first semiconductor die and the second semiconductor die, the first dielectric material layer having a first density; and depositing a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a second density different than the first density, and the second dielectric material layer including a void region (see claim 1, U.S. Patent No. 12,381,181) .
Claim 1: “ A method of forming a semiconductor device, the method comprising: mounting a first semiconductor die on a support substrate … mounting a second semiconductor die on the support substrate, such that the first semiconductor die and the second semiconductor die are separated …forming a first dielectric material layer between the first semiconductor die and the second semiconductor die, the first dielectric material layer having a first density; and forming a second dielectric material layer on the first dielectric material layer, the second dielectric material layer having a second density different than the first density, and the second dielectric material layer including a void region”.
2. The method of claim 1, wherein depositing the first dielectric material layer comprises depositing the first dielectric material layer over an upper surface and at least one side surface of the first semiconductor die, over an upper surface and at least one side surface of the second semiconductor die, and over the substrate in a gap between the first semiconductor die and the second semiconductor die, and wherein the second dielectric material layer is deposited over the first dielectric material layer so as to form the void region (see claim 2, U.S. Patent No. 12,381,181) .).
Claim 2: The method of claim 1, wherein the forming of the first dielectric material layer comprises depositing the first dielectric material layer on the first semiconductor die and the second semiconductor die, and between the first semiconductor die and the second semiconductor die, and wherein the forming of the second dielectric material layer comprises depositing the second dielectric material layer on the first dielectric material layer so as to form the void region.
Claim 3: The method of claim 2, further comprising: planarizing the first dielectric material layer and the second dielectric material layer to form an upper surface of the first dielectric material layer and an upper surface of the second dielectric material layer that is co-planar with the upper surface of the first dielectric material layer (see claim 3, U.S. Patent No. 12,381,181).
Claim 3: The method of claim 2, further comprising: planarizing the first dielectric material layer and the second dielectric material layer to form an upper surface of the first dielectric material layer and an upper surface of the second dielectric material layer that is co-planar with the upper surface of the first dielectric material layer.
4. The method of claim 3, wherein the first dielectric material layer and the second dielectric material layer are planarized to remove the first dielectric material layer and the second dielectric material layer from over the upper surface of the first semiconductor die and from over the upper surface of the second semiconductor die such that the upper surfaces of the first semiconductor die, the second semiconductor die, the first dielectric material layer and the second dielectric material layer are co-planar (see claim 3 of U.S. Patent No. 12,381,181, it provides the same meaning and result in claim 4 of the present invention).
Claim 3: The method of claim 2, further comprising: planarizing the first dielectric material layer and the second dielectric material layer to form an upper surface of the first dielectric material layer and an upper surface of the second dielectric material layer that is co-planar with the upper surface of the first dielectric material layer.
Claim 8: The method of claim 1, wherein each of the first dielectric material layer and the second dielectric material layer comprises one of undoped silicon glass (USG), fluorosilicate glass (FSG), SiC, SiON, SiN, SiCN, a low-K film, an extreme low-K (ELK) film, phosphor-silicate glass (PSG) and tetra-ethoxy-silane (TEOS) (see claim 6, U.S. Patent No. 12,381,181).
Claim 6: The method of claim 1, wherein each of the first dielectric material layer and the second dielectric material layer comprises one of undoped silicon glass (USG), fluorosilicate glass (FSG), SiC, SiON, SiN, SiCN, a low-K film, an extreme low-K (ELK) film, phosphor-silicate glass (PSG) and tetra-ethoxy-silane (TEOS).
Claim 9: The method of claim 1, wherein the void region comprises one of air, nitrogen, and a dielectric material including one of undoped silicon glass (USG), fluorosilicate glass (FSG), SiC, SiON, SiN, SiCN, a low-K film, an extreme low-K (ELK) film, phosphor-silicate glass (PSG) and tetra-ethoxy-silane (TEOS) (see claim 7, U.S. Patent No. 12,381,181).
Claim 7: The method of claim 1, wherein the void region comprises one of air, nitrogen, and a dielectric material including one of undoped silicon glass (USG), fluorosilicate glass (FSG), SiC, SiON, SiN, SiCN, a low-K film, an extreme low-K (ELK) film, phosphor-silicate glass (PSG) and tetra-ethoxy-silane (TEOS).
Claims 10 and 11: A method of forming a semiconductor device, the method comprising: depositing a first dielectric material over a first semiconductor die and a second semiconductor die and within a gap between the first semiconductor die and the second semiconductor die; and depositing a second dielectric material over the first dielectric material layer within the gap between the first semiconductor die and the second semiconductor die, the second dielectric material including a void region located between the first semiconductor die and the second semiconductor die; and wherein the second dielectric material has a physical property that is different from a physical property of the first dielectric material. (see claim 9, U.S. Patent No. 12,381,181).
Claim 9: “A method of forming a semiconductor device, the method comprising: forming a first dielectric material within a gap between a first semiconductor die and a second semiconductor die…and forming a second dielectric material over the first dielectric material layer within the gap between the first semiconductor die and the second semiconductor die, the second dielectric material having a physical property that is different from a physical property of the first dielectric material, and the second dielectric material including a void region located between the first semiconductor die and the second semiconductor die”.
Claim 12: The method of claim 10, wherein the second dielectric material has at least one of a density and a coefficient of thermal expansion that is different from a density and/or a coefficient of thermal expansion of the first dielectric material (see claim 11, U.S. Patent No. 12,381,181).
Claim 11: The method of claim 9, wherein the second dielectric material has a coefficient of thermal expansion that is different from the coefficient of thermal expansion of the first dielectric material.
Claim 13: The method of claim 10, wherein the first semiconductor die comprises a first semiconductor substrate and the second semiconductor die comprises a second semiconductor substrate, wherein depositing the first dielectric material within the gap between the first semiconductor die and the second semiconductor die comprises depositing the first dielectric material such that an upper surface of the first dielectric material within the gap is vertically below an uppermost surface of the first semiconductor substrate and an upper most surface of the second semiconductor substrate (see claim 9, U.S. Patent No. 12,381,181)..
Claim 9: “A method of forming a semiconductor device, the method comprising: forming a first dielectric material within a gap between a first semiconductor die and a second semiconductor die, the first semiconductor die comprising a first semiconductor substrate…nd the second semiconductor die comprising a second semiconductor substrate”.
Claim 14: The method of claim 13, wherein: depositing the second dielectric material comprises depositing the second dielectric material over the first dielectric material such that a remaining volume of the gap between the first semiconductor die and the second semiconductor die is filled by the second dielectric material and the void region (see claim 12, U.S. Patent No. 12,381,181).
Claim 12: The method of claim 9, wherein forming the first dielectric material comprises depositing the first dielectric material over the first semiconductor die and the second semiconductor die and partially filling the gap between the first semiconductor die and the second semiconductor die, and forming the second dielectric material comprises depositing the second dielectric material over the first dielectric material such that a remaining volume of the gap between the first semiconductor die and the second semiconductor die is filled by the second dielectric material and the void region.
Claim 15: A method of forming a semiconductor device, the method comprising: depositing a first dielectric material to partially fill a gap between a first semiconductor die and a second semiconductor die; and depositing a second dielectric material over the first dielectric material layer within the gap between the first semiconductor die and the second semiconductor die, wherein depositing the second dielectric material comprises controlling a processing condition during the deposition such that a remaining volume of the gap between the first semiconductor die and the second semiconductor die is filled by the second dielectric material and a void region located within the second dielectric material (see claims 15 and 19, U.S. Patent No. 12,381,181).
Claims 15 and 19: A method of forming a semiconductor device, the method comprising: depositing a first dielectric material within a gap between a first semiconductor die and a second semiconductor die, the first semiconductor die comprising a first semiconductor substrate, a first intermetal dielectric over the first semiconductor substrate, and first metal lines and first metal vias within the first intermetal dielectric and the second semiconductor die comprising a second semiconductor substrate, a second intermetal dielectric over the second semiconductor substrate, and second metal lines and second metal vias within the second intermetal dielectric; and depositing a second dielectric material over the first dielectric material layer within the gap between the first semiconductor die and the second semiconductor die, wherein depositing the second dielectric material comprises controlling a processing condition during the deposition such that a void region is formed within the second dielectric material; and
wherein the first dielectric material is deposited to partially fill the gap between the first semiconductor die and the second semiconductor die, and the second dielectric material is deposited over the first dielectric material such that a remaining volume of the gap between the first semiconductor die and the second semiconductor die is filled by the second dielectric material and the void region.
Claim 16: The method of claim 15, wherein controlling the processing condition during the deposition of the second dielectric material comprises at least one of controlling a pressure, a temperature, a deposition rate, and a gas flow rate during the deposition of the second dielectric material such that the void region is formed within the second dielectric material (see claim 16, U.S. Patent No. 12,381,181).
Claim 16: The method of claim 15, wherein controlling the processing condition during the deposition of the second dielectric material comprises at least one of controlling a pressure, a temperature, a deposition rate, and a gas flow rate during the deposition of the second dielectric material such that the void region is formed within the second dielectric material.
Claim 18: The method of claim 16, wherein the processing condition during the deposition of the second dielectric material is controlled such that an entire periphery of the void region is bounded by the second dielectric material (see claims 16 and 17, U.S. Patent No. 12,381,181).
Claims 16 and 17: The method of claim 15, wherein controlling the processing condition during the deposition of the second dielectric material comprises at least one of controlling a pressure, a temperature, a deposition rate, and a gas flow rate during the deposition of the second dielectric material such that the void region is formed within the second dielectric material;
wherein an entire periphery of the void region is bounded by the second dielectric material.
Claim 19: The method of claim 16, wherein the processing condition during the deposition of the second dielectric material is controlled such that the void region does not extend above an upper surface of the first semiconductor die or an upper surface of the second semiconductor die (see claim 15, U.S. Patent No. 12,381,181).
Claim 15: “A method of forming a semiconductor device, the method comprising: …wherein depositing the second dielectric material comprises controlling a processing condition during the deposition such that a void region is formed within the second dielectric material”.
Claim 20: The method of claim 15, wherein the first dielectric material and the second dielectric material differ from one another with respect to at least one of density and coefficient of thermal expansion (see claim 18, U.S. Patent No. 12,381,181).
Claim 18: The method of claim 15, wherein the first dielectric material and the second dielectric material differ from one another with respect to at least one of density and coefficient of thermal expansion.
Allowable Subject Matter
Claims 5-7, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 22, 2026
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