DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claims 19-20 are objected to because of the following informalities: “an expose the” should likely read -- and expose the --. Appropriate correction is required.
Claim 20 inherits this objection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 8) It is unclear how many “upper surface of the fourth dielectric layer” are required as “an upper surface of the fourth dielectric layer” is recited twice.
During examination, “an upper surface of the fourth dielectric layer” subsequent to the first one were read as “the upper surface of the fourth dielectric layer”.
(Re Claim 9) “the conductive trench” lacks antecedence.
During examination, this was read as “the conductive via”.
Claims 10-15 inherit this rejection for indefiniteness.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276).
(Re Claim 1) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (see abstract, Fig. 5B, ¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not disclosed.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look to related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 (Fig. 9) that has a first dielectric layer 204 deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 over a copper metallization layer (Fig. 5B, ¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers, the first metal interconnect feature will naturally have hillocks, the first dielectric layer and second dielectric layers will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
The localized elevated region respective to the second dielectric layer is removed due to planarization (Yang: Fig. 9).
Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device.
Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C).
A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overlie a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
With the described utilization of the structure of Yang by Ponoth, modified Ponoth then teaches a method of forming an interconnect structure for an integrated circuit device, comprising: forming a first dielectric layer (Yang: 204; Fig. 9) and a second dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9, corresponds with 501 of Ponoth, Fig. 5B) over a first metal interconnect feature (Fig. 5B markup) of the integrated circuit device, where the first dielectric layer and the second dielectric layer each include respective localized elevated regions overlying a hillock of the first metal interconnect feature (due to pattern transfer, each will have a hump overlying the hillock that forms as taught by Chambers and described above); performing a planarization process (Yang: ¶44) to remove the localized elevated region of the second dielectric layer and form a planar upper surface of the second dielectric layer overlying the localized elevated region of the first dielectric layer and the hillock; forming a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) and a fourth dielectric layer (Ponoth: 511+520+521; Fig. 5B markup) over the planar upper surface of the second dielectric layer (Ponoth: Fig. 5B); performing an etching process through the fourth dielectric layer, the third dielectric layer, and into the second dielectric layer to form a trench (coextensive with the second metal interconnect feature identified in the Fig. 5B markup) having a planar bottom surface (bottommost surface) overlying the localized elevated region of the first dielectric layer and the hillock (Ponoth: Fig. 5B, ¶42); and forming a second metal interconnect feature (Fig. 5B) within the trench, the second metal interconnect feature having a planar bottom surface (bottommost surface) overlying the localized elevated region of the first dielectric layer and the hillock (as discussed with respect to Chambers).
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(Re Claim 5) Modified Ponoth teaches the method of claim 1, wherein the second metal interconnect feature is formed in a first region (a region with an area coextensive with the second metal interconnect feature at its widest, with a thickness from the bottom of the first dielectric layer to the top of the fourth dielectric layer) of the integrated circuit device; and there is a second region (the remaining part of the integrated circuit device) of the integrated circuit device.
Modified Ponoth has not been shown explicitly to teach the method further comprises: prior to performing the planarization process, performing an etching process through the second dielectric layer and the first dielectric layer to form a via opening in a second region of the integrated circuit device; and forming a conductive via in the via opening.
Yang teaches, prior to performing the planarization process, performing an etching process through the second dielectric layer (205; Fig. 2) and the first dielectric layer (204; Fig. 2) to form a via opening (the etched region with widths shown by 210 and 212; Fig. 2); and forming a conductive via (leftmost 801+802 metal structure of Yang; Fig. 9) in the via opening.
From the discussion with respect to Yang’s structure in the rejection of claim 1, and that directly above, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to make further metal interconnect features extending into the second dielectric layer 501 of Ponoth in order to form more electrical connections with devices in the material. Therefore, a PHOSITA would find it obvious to form another metal interconnect, at this point a third metal interconnect structure, so as to connect with the underlying conductive via (leftmost 801+802 metal structure of Yang; Fig. 9) of the metallization of Yang. From Yang, the conductive via 801+802 extends between the third metal interconnect feature identified in the Fig. 5B markup and the first metal interconnect feature 201 of Yang, and the conductive via is laterally surrounded by the second dielectric layer 501 of Ponoth and the first dielectric layer 204 of Yang (Yang: Fig. 9).
The conductive via of modified Ponoth is then formed in the via opening prior to the planarization process as claimed, as shown by Yang, and the second region is then a region with an area coextensive with the third metal interconnect structure as identified in the Fig. 5B markup at its widest, with a thickness from the bottom of the first dielectric layer to the top of the fourth dielectric layer.
(Re Claim 6) Modified Ponoth teaches the method of claim 5, wherein forming a conductive via comprises: depositing a barrier layer (Yang: 801; Fig. 8) over an upper surface of the second dielectric layer, over sidewalls (left and right sidewalls; Fig. 8) of the via opening, and over an exposed portion (in the width shown as 812; Fig. 2 and 8) of the first metal interconnect feature at the bottom of the via opening; and depositing a metallic fill layer (802; Fig. 8) over the barrier layer and within a remaining volume of the via opening (Fig. 8), wherein the planarization process removes portions of the barrier layer and the metallic fill layer from above an upper surface of the second dielectric layer (compare Fig. 8 to 9; ¶44).
(Re Claim 7) Modified Ponoth teaches the method of claim 6, wherein the trench formed in the first region of the integrated circuit device is a first trench (coextensive with the identified trench), and wherein performing the etching process further comprises etching through the fourth dielectric layer, the third dielectric layer, and into the second dielectric layer to form a second trench (coextensive with the third metal interconnect structure; Fig. 5B) in the second region of the integrated circuit device, the second trench having a planar bottom surface that exposes an upper surface (topmost surface) of the conductive via (Yang’s 801+802; Fig. 9), and a third metal interconnect structure is formed within the second trench (Fig. 5B markup).
(Re Claim 8) Modified Ponoth teaches the method of claim 7, but has not been explicitly shown to teach forming the second metal interconnect structure and the third metal interconnect structure comprises: depositing a barrier layer over an upper surface of the fourth dielectric layer, and over the sidewalls and the bottom surfaces of each of the first and second trenches; depositing a metallic fill layer over the barrier layer and within the remaining volumes of the first and second trenches; and performing a planarization process to remove the barrier layer and the metallic fill layer from over an upper surface of the fourth dielectric layer to form the second metal interconnect structure in the first trench and the third metal interconnect structure in the second trench, wherein the third metal interconnect structure is electrically connected to the first metal interconnect structure by the conductive via, and the second metal interconnect structure is electrically isolated from the first metal interconnect structure by the second dielectric layer and the first dielectric layer.
Ponoth teaches filling trenches (multiple openings; Fig. 6, ¶44) after their formation with conductive materials.
Yang teaches depositing a barrier layer (Yang: 801; Fig. 8) over an upper surface (top surface; Fig. 8) of a dielectric layer (205; Fig. 8), and over sidewalls (left and right) and bottom surfaces (bottommost) of first and second trenches (first trench is coextensive with the middle 802; second trench is coextensive with the leftmost 801+802);
depositing a metallic fill layer (802; Fig. 8) over the barrier layer and within the remaining volumes of the first and second trenches (Fig. 8); and
performing a planarization process to remove the barrier layer and the metallic fill layer from over an upper surface of the dielectric layer to form a metal interconnect structure (801+802; Fig. 9).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to deposit a barrier layer over an upper surface (top; Fig. 5B markup) of the fourth dielectric layer, and over the sidewalls and the bottom surfaces of each of the first and second trenches; depositing a metallic fill layer over the barrier layer and within the remaining volumes of the first and second trenches; and performing a planarization process to remove the barrier layer and the metallic fill layer from over the upper surface of the fourth dielectric layer to form the second metal interconnect structure in the first trench and the third metal interconnect structure in the second trench as a consequence of removing excess material, as taught by Yang. Barrier layers are standard practice (Ponoth: ¶42) and reduce diffusion of metals; and planarization prepares the surface of the fourth dielectric layer for further processing while electrically separating the metal interconnect structures (Yang: ¶¶44, 46).
After the planarization process, the third metal interconnect structure is electrically connected to the first metal interconnect structure by the conductive via (as described in the rejection of claim 5), and the second metal interconnect structure is electrically isolated from the first metal interconnect structure by the second dielectric layer and the first dielectric layer (Yang: Fig. 9; Fig. 5B markup).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276) as applied to claim 1 above, and further in view of Ruan et al. (US 2008/0150131).
(Re Claim 2) Modified Ponoth teaches the method of claim 1, but has not been shown explicitly to teach the hillock has at least one of a height and a width dimension of at least 50 nm.
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
With Ruan’s hillock values available, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276) as applied to claim 1 above, and further in view of Liu et al. (US 2009/0137119) and Shimabukuro et al. (US 2020/0006131).
(Re Claim 3) Modified Ponoth teaches the method of claim 1, but has not been explicitly shown to teach the first dielectric layer and the third dielectric layer are etch stop dielectric layers having a higher etch resistance to an etch chemistry used during the etching process than the second dielectric layer and the fourth dielectric layer, the second dielectric layer and the fourth dielectric layer having a greater thickness than the first dielectric layer and the third dielectric layer.
Ponoth teaches that a third dielectric layer (310; Fig. 3C) has a higher etch resistance than a fourth dielectric layer (311; Fig. 3C) to an etch chemistry (selective etching of 311 compared to 310 in Fig. 3C; ¶¶35-37) during an etching process.
A PHOSITA would find it obvious to have the third dielectric layer have a higher etch resistance to an etch chemistry using during the etching process to clear the fourth dielectric layer above the third dielectric layer, in the manner taught by Ponoth’s Fig. 3C (¶¶35-37), to control the depth of features (¶35).
Ponoth teaches a third dielectric layer (310; Fig. 3C) serves as an etch stop layer (“the selective-etching process may stop at capping layer 310”; ¶37).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the third dielectric layer 510 of modified Ponoth as an etch stop layer to allow for depth control while etching trenches (Ponoth: ¶¶35-37).
Yang teaches that the first dielectric layer serves as an etch stop layer (¶31).
Liu teaches forming a dielectric layer (28; Fig. 3) using an undoped silicate glass (¶24), and an etch stop layer (26; Fig. 3) formed using silicon nitride (¶24).
A PHOSITA would find it obvious to form the second and fourth dielectric layer using undoped silicate glass as taught by Liu, due to its good thermal stability.
Furthermore, a PHOSITA would find it obvious to use silicon nitride to form the first dielectric layer (Fig. 5B markup of Ponoth), third dielectric layer (Fig. 5B markup of Ponoth), and fifth dielectric layer (520; Fig. 5B markup of Ponoth) using silicon nitride due to its suitability as an etch stop layer for layers of undoped silicate glass (Liu: ¶24).
As the first and third dielectric layers are made from the same material, and the second and fourth dielectric layer are made from the same material, the first and third dielectric layers are etch stop layers having a higher etch resistance to the etch chemistry using during the etching process than the second dielectric layer and the fourth dielectric layer.
Yang teaches a suitable thickness for an etch stop layer made of silicon nitride is from about 3 to about 100 nm (¶24). The first, third, and fifth dielectric layer are etch stops formed of silicon nitride.
Shimabukuro teaches forming a dielectric layer (690; Fig. 4) formed of undoped silicate glass with a thickness of 100 nm to 800 nm (¶¶37, 45). The second and fourth dielectric layers are formed of undoped silicate glass.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Therefore, a PHOSITA would find it obvious to form respective material layers having the dimensions found in Shimabukuro and Yang, resulting in the second dielectric layer and the fourth dielectric layer having a greater thickness than the first dielectric layer and the third dielectric layer.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276) as applied to claim 1 above, and further in view of Drizlikh et al. (US 7,504,304), and Dunn et al. (US 2011/0091815).
(Re Claim 4) Modified Ponoth teaches the method of claim 1, but has not been shown to explicitly teach performing the etching process comprises etching into the second dielectric layer to form the trench such that a depth of the bottom surface of the trench beneath a bottom surface of the third dielectric layer is at least about 10% of a total thickness of the second dielectric layer.
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30)
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form trenches in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each trench are result effective variables of the etch depth; the etch rate will be faster for wider trenches on the lowest level of Ponoth; the trenches used to form a second and third metal interconnect feature may be wider than most or all of the other trenches formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between the bottom surface of the trench and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
The depth is between the bottom surface of the trench beneath a bottom surface (bottommost) of the third dielectric layer.
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276).
(Re Claim 9) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (see abstract, Fig. 5B, ¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not disclosed.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look to related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 (Fig. 9) that has a first dielectric layer 204 deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 over a copper metallization layer (Fig. 5B, ¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers, the first metal interconnect feature will naturally have hillocks, the first dielectric layer and second dielectric layers will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
The second local elevated region respective to the second dielectric layer is removed due to planarization (Yang: Fig. 9).
Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device.
Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C).
A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overlie a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
Yang teaches, prior to performing the planarization process, performing an etching process through the second dielectric layer (205; Fig. 2) and the first dielectric layer (204; Fig. 2) to form a via opening (the etched region with widths shown by 210 and 212; Fig. 2); and forming a conductive via (leftmost 801+802 metal structure of Yang; Fig. 9) in the via opening.
From the discussion with respect to Yang’s structure in the rejection of claim 1, and that directly above, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to make further metal interconnect features extending into the second dielectric layer 501 of Ponoth in order to form more electrical connections with devices in the material. Therefore, a PHOSITA would find it obvious to form another metal interconnect, at this point a third metal interconnect structure, so as to connect with the underlying conductive via (leftmost 801+802 metal structure of Yang; Fig. 9) of the metallization of Yang. From Yang, the conductive via 801+802 extends between the third metal interconnect feature identified in the Fig. 5B markup and the first metal interconnect feature 201 of Yang, and the conductive via is laterally surrounded by the second dielectric layer 501 of Ponoth and the first dielectric layer 204 of Yang (Yang: Fig. 9).
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
The conductive via of modified Ponoth is then formed in the via opening prior to the planarization process as claimed, as shown by Yang, and the second region is then a region with an area coextensive with the third metal interconnect structure as identified in the Fig. 5B markup at its widest, with a thickness from the bottom of the first dielectric layer to the top of the fourth dielectric layer.
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
For the same reason that the first and second local elevated region are formed, as a consequence of blanket deposition of the conductive material used to form the conductive via, due to pattern transfer a third local elevated region will form before planarization overlying the hillock, which is removed due to performing the planarization process.
With the described utilization of the structure of Yang by Ponoth, modified Ponoth teaches a method of forming an interconnect structure for an integrated circuit device, comprising, comprising: forming a first dielectric layer (Yang: 204; Fig. 9) over a first metal interconnect feature (Yang: 210; Fig. 9) comprising a hillock (Chambers: hillocks) in a first region (a region with an area coextensive with the second metal interconnect feature at its widest, with a thickness from the bottom of the first dielectric layer to the top of the fourth dielectric layer), wherein the first dielectric layer comprises a first local elevated region overlying the hillock (due to pattern transfer, the first dielectric layer will have a hump overlying the hillock that forms as taught by Chambers and described above); forming a second dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9, corresponds with 501 of Ponoth, Fig. 5) over the first dielectric layer (Yang: 204: Fig. 9), wherein the second dielectric layer comprises a second local elevated region (due to pattern transfer, the second dielectric layer will have a hump overlying the hillock that forms as taught by Chambers and described above) overlying the first local elevated region; forming an opening (Yang: the etched region with widths shown by 210 and 212; Fig. 2) through the first dielectric layer and the second dielectric layer in a second region (the region with an area coextensive with the third metal interconnect structure as identified in the Fig. 5B markup at its widest, with a thickness from the bottom of the first dielectric layer to the top of the fourth dielectric layer) wherein the first metal interconnect feature is exposed in the bottom of the opening (Yang: Fig. 2); depositing a conductive material (Yang: 802; Fig. 8) over the second dielectric layer and within the opening, wherein the conductive material comprises a third local elevated region (as a consequence of pattern transfer, the conductive material will have a hump matching the shape of the hillock) overlying the first local elevated region and the second local elevated region; performing a planarization process (Yang: Fig. 9) to remove the conductive material from over the upper surface of the second dielectric layer and to remove the second local elevated region of the second dielectric layer to provide a planar upper surface of the second dielectric layer and a conductive via in the second region laterally surrounded by the first dielectric layer and the second dielectric layer and contacting the first metal feature (Yang: Fig. 9); forming a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) over the planar upper surface of the second dielectric layer and an upper surface of the conductive via (Ponoth: Fig. 5B); forming a fourth dielectric layer (Ponoth: 511+520+521; Fig. 5B) over the third dielectric layer; forming a first trench (the opening coextensive with the second metal interconnect feature; Fig. 5B markup) through the fourth dielectric layer and the third dielectric layer in the first region and a second trench (the opening coextensive with the third metal interconnect feature; Fig. 5B) through the fourth dielectric layer and the third dielectric layer in the second region, wherein a bottom surface of the first trench overlies the first local elevated region of the first dielectric layer (as described above with respect to Chambers), and the upper surface of the conductive trench is exposed in a bottom surface of the second trench (Ponoth: Fig. 5B markup); and depositing a conductive material (Ponoth: ¶42) in the first trench and in the second trench to form a second metal interconnect feature overlying the first local elevated region of the first dielectric layer in the first region and a third metal interconnect feature in the second region, wherein the third metal interconnect feature is electrically coupled to the first metal interconnect feature by the conductive via (as described above with respect to Yang’s conductive via).
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(Re Claim 14) Modified Ponoth teaches the method of claim 9, but has not been shown explicitly to teach depositing the conductive material in the first trench and the second trench comprises: depositing a first conductive material over an upper surface of the fourth dielectric layer, over the fourth dielectric layer, the third dielectric layer, and the second dielectric layer along sidewalls of the first trench and the second trench, over the second dielectric layer along a bottom surface of the first trench, and over the second dielectric layer and the upper surface of the conductive via along a bottom surface of the second trench; depositing a second conductive material over the first conductive material to fill a remaining volume of the first trench and a remaining volume of the second trench; and performing a planarization process to remove the first conductive material and the second conductive material from over the fourth dielectric layer.
Ponoth teaches filling trenches (multiple openings; Fig. 6, ¶44) after their formation with conductive materials.
Yang teaches depositing a first conductive material (Yang: 801; Fig. 8) over an upper surface (top surface; Fig. 8) of a dielectric layer (205; Fig. 8), and over sidewalls (left and right) and bottom surfaces (bottommost) of first and second trenches (first trench is coextensive with the middle 802; second trench is coextensive with the leftmost 801+802; the deposition of the first conductive material is shown to be conformal);
depositing a second conductive material (802; Fig. 8) over the first conductive material to fill a remaining volume of the first and second trenches (Fig. 8); and
performing a planarization process to remove the first conductive material and the second conductive material from over an upper surface of the dielectric layer to form a metal interconnect structure (801+802; Fig. 9).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to deposit a first conductive material over an upper surface (top; Fig. 5B markup) of the fourth dielectric layer, over the fourth dielectric layer, the third dielectric layer, and the second dielectric layer along a bottom surface of the first trench, and over the second dielectric layer and the upper surface of the conductive via along a bottom surface of the second trench; depositing a second conductive material over the first conductive material to fill the remaining volumes of the first and second trenches; and performing a planarization process to remove the first and second conductive material from over the upper surface of the fourth dielectric layer to form the second metal interconnect structure in the first trench and the third metal interconnect structure in the second trench as a consequence of removing excess material, as taught by Yang. First conductive layers functioning as barrier layers are standard practice (Ponoth: ¶42) and reduce diffusion of metals; and planarization prepares the surface of the fourth dielectric layer for further processing while electrically separating the metal interconnect structures (Yang: ¶¶44, 46).
After the planarization process, the third metal interconnect structure is electrically connected to the first metal interconnect structure by the conductive via (as described in the rejection of claim 5), and the second metal interconnect structure is electrically isolated from the first metal interconnect structure by the second dielectric layer and the first dielectric layer (Yang: Fig. 9; Fig. 5B markup).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276) as applied to claim 9 above, and further in view of Liu et al. (US 2009/0137119) and Shimabukuro et al. (US 2020/0006131).
(Re Claim 10) Modified Ponoth teaches the method of claim 9, not been explicitly shown to teach the third dielectric layer and the fourth dielectric layer have different compositions, and forming the first trench and the second trench comprises: performing a first etching process through the fourth dielectric layer to expose the third dielectric layer at the bottom of the first trench and the second trench; and performing a second etching process through the third dielectric layer and into the second dielectric layer such that the second dielectric layer is exposed at the bottom of the first trench and the second trench.
Ponoth teaches that a third dielectric layer (310; Fig. 3C) has a higher etch resistance than a fourth dielectric layer (311; Fig. 3C) to an etch chemistry (selective etching of 311 compared to 310 in Fig. 3C; ¶¶35-37) during an etching process.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to have the third dielectric layer have a higher etch resistance to an etch chemistry using during the etching process to clear the fourth dielectric layer above the third dielectric layer, in the manner taught by Ponoth’s Fig. 3C (¶¶35-37), to control the depth of features (¶35).
Ponoth teaches a third dielectric layer (310; Fig. 3C) serves as an etch stop layer (“the selective-etching process may stop at capping layer 310”; ¶37).
A PHOSITA would find it obvious to form the third dielectric layer 510 of modified Ponoth as an etch stop layer to allow for depth control while etching trenches (Ponoth: ¶¶35-37).
Yang teaches that the first dielectric layer serves as an etch stop layer (¶31).
Liu teaches forming a dielectric layer (28; Fig. 3) using an undoped silicate glass (¶24), and an etch stop layer (26; Fig. 3) formed using silicon nitride (¶24).
A PHOSITA would find it obvious to form the second and fourth dielectric layer using undoped silicate glass as taught by Liu, due to its good thermal stability.
Furthermore, a PHOSITA would find it obvious to use silicon nitride to form the first dielectric layer (Fig. 5B markup of Ponoth), third dielectric layer (Fig. 5B markup of Ponoth), and fifth dielectric layer (520; Fig. 5B markup of Ponoth) using silicon nitride due to its suitability as an etch stop layer for layers of undoped silicate glass (Liu: ¶24).
The third dielectric layer and fourth dielectric layer now have different compositions.
Ponoth teaches forming a first trench (312b; Fig. 3C) and second trench (313b; Fig. 3C), where forming comprising performing a first etching process through a fourth dielectric layer (311; Fig. 3C) to expose a third dielectric layer (310; Fig. 3C) at the bottom of the first trench and the second trench; and
performing a second etching process (“capping layer 310 at the bottom of 312b may be removed if it still remains”; ¶37) through the third dielectric layer (“capping layer 310 at the bottom of 312b may be removed if it still remains” (¶37); “etch capping layer 310 as well and therefore may expose conductive stud 302” (¶36)).
A PHOSITA would find it obvious to etch through the fourth dielectric layer to expose the third dielectric layer of modified Ponoth using a first etching process, and then etch through the third dielectric layer using a second etching process as taught by Ponoth’s Fig. 3C embodiment, to allow for controlling the depths of metal features (¶¶29, 35).
Ponoth teaches that “trenches of different widths are preferably formed and sometimes required to be formed at approximately the same depth, therefore having the same contrast, in order for them to interact properly and/or function efficiently.” (¶29).
As is shown in Ponoth’s Fig. 5B, it would be obvious to continue the second etching process through the third dielectric and into the second dielectric such that the second dielectric is exposed at the bottom of the first trench and the second trench, as overetching into the second dielectric for both trenches ensures features smaller than the first and second trenches at the depth below Ponoth’s 520 have their corresponding portions of the third dielectric layer removed to allow for connections from within the second dielectric to be routed outside it. Smaller features etch slower than larger ones (Ponoth: Fig. 7, ¶¶44-45), and it is preferred for trenches of different sizes to be formed at any one depth.
(Re Claim 11) Modified Ponoth teaches the method of claim 10, wherein the third dielectric layer comprises an etch stop layer having a higher etch resistance (silicon nitride serves as an etch stop when selectively etching undoped silicate glass; Liu: ¶24) than the fourth dielectric layer to an etch chemistry used during the first etching process.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276), Liu et al. (US 2009/0137119) and Shimabukuro et al. (US 2020/0006131), as applied to claim 10 above, and further in view of Drizlikh et al. (US 7,504,304), and Dunn et al. (US 2011/0091815).
(Re Claim 12) Modified Ponoth teaches the method of claim 10, but has not been shown explicitly to teach a bottom surface of the first trench and a bottom surface of the second trench are recessed relative to the bottom surface of the third dielectric layer by at least 10% of a maximum distance between the bottom surface of the third dielectric layer and an upper surface of the first dielectric layer.
Modified Ponoth teaches a bottom surface (bottommost) of the first trench and a bottom surface (bottommost) of the second trench; and an upper surface (uppermost) of the first dielectric layer.
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30).
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form trenches in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each trench are result effective variables of the etch depth; the etch rate will be faster for wider trenches on the lowest level of Ponoth; the trenches used to form a second and third metal interconnect feature may be wider than most or all of the other trenches formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between the bottom surface of the trench and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Modified Ponoth teaches a bottom surface (bottommost) of the first trench and a bottom surface (bottommost) of the second trench; and an upper surface (uppermost) of the first dielectric layer.
(Re Claim 13) Modified Ponoth teaches the method of claim 12, but has not been shown to teach a bottom surface of the first trench and a bottom surface of the second trench are recessed relative to the bottom surface of the third dielectric layer by at least 20% of a maximum distance between the bottom surface of the third dielectric layer and an upper surface of the first dielectric layer.
Modified Ponoth teaches a bottom surface (bottommost) of the first trench and a bottom surface (bottommost) of the second trench; and an upper surface (uppermost) of the first dielectric layer.
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30)
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form trenches in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each trench are result effective variables of the etch depth; the etch rate will be faster for wider trenches on the lowest level of Ponoth; the trenches used to form a second and third metal interconnect feature may be wider than most or all of the other trenches formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between the bottom surface of the trench and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), and Yang et al. (US 2007/0040276), as applied to claim 9 above, and further in view of Ruan et al. (US 2008/0150131).
(Re Claim 15) Modified Ponoth teaches the method of claim 9, but has not been shown explicitly to teach the local elevated region of the first dielectric layer has a height of at least 50 nm, and a bottom surface of the first trench overlying the local elevated region of the first dielectric layer comprises a planar surface.
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
With Ruan’s hillock values available, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276), Ruan et al. (US 2008/0150131), Drizlikh et al. (US 7,504,304), and Dunn et al. (US 2011/0091815).
(Re Claim 16) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (see abstract, Fig. 5B, ¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not disclosed.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look to related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 (Fig. 9) that has a first dielectric layer 204 deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 over a copper metallization layer (Fig. 5B, ¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers, the first metal interconnect feature will naturally have hillocks, the first dielectric layer and second dielectric layers will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
The second local elevated region respective to the second dielectric layer is removed due to planarization (Yang: Fig. 9).
Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device.
Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C).
A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overlie a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
A first elevated region is the part of the first dielectric that spans the width of the hillock. As there will be pattern transfer due to the hillock into layers overlying the identified first metal interconnect feature (Chambers: Fig. 3B and 3C), the hillock will cause a region directly over the hillock to have a height above that of the flat part of the deposited first dielectric layer that matches the hillock’s height.
With Ruan’s hillock values available, and therefore the height of a first elevated region, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30).
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form trenches in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each trench are result effective variables of the etch depth; the etch rate will be faster for wider trenches on the lowest level of Ponoth; the trenches used to form a second and third metal interconnect feature may be wider than most or all of the other trenches formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical etch depth into the second dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With the described utilization of the structure of Yang by Ponoth, modified Ponoth teaches a method of forming an interconnect structure for an integrated circuit device, comprising, comprising: forming a first dielectric layer (Yang: 204; Fig. 9) comprising a first local elevated region (the part of the first dielectric layer that spans the width of the hillock) having a height of at least 50 nm (see discussion of Ruan); forming a second dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9 corresponds with 501 of Ponoth, Fig. 5) over the first dielectric layer such that a second local elevated region (the part of the second dielectric layer that spans the width of the first local elevated region and is above the horizontal top surface of the second dielectric layer) is formed in the second dielectric layer overlying the first local elevated region; performing a planarization process (Yang: Fig. 9) to remove the second local elevated region of the second dielectric layer to provide a planar upper surface of the second dielectric layer (Yang: Fig. 9); forming a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) over the planar upper surface of the second dielectric layer; forming a fourth dielectric layer (Ponoth: 511+520+521; Fig. 5B) over the third dielectric layer; performing an etching process through the fourth dielectric layer, the third dielectric layer and into the second dielectric layer (Ponoth: Fig. 5B) by at least 10% of a maximum thickness of the second dielectric layer (see optimization discussion above) between a lower surface (lowermost) of the third dielectric layer and an upper surface (uppermost) of the first dielectric layer to form a trench (coextensive with the opening formed for the identified second metal interconnect structure in the Fig. 5B markup) having a planar bottom surface (bottommost) overlying the first local elevated region of the first dielectric layer (Ponoth: Fig. 5B markup); depositing a conductive material (Ponoth: 512; Fig. 5B and 5B markup, ¶42) in the trench to form a metal interconnect feature (the second metal interconnect structure identified above and in the Fig. 5B markup) having a planar bottom surface (Ponoth: Fig. 5B) overlying the first local elevated region of the first dielectric layer (Fig. 5B markup).
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(Re Claim 17) Modified Ponoth teaches the method of claim 16, wherein the second dielectric layer continuously contacts the planar bottom surface of the metal interconnect feature (Fig. 5B) between a first edge (leftmost edge; Fig. 5B ) and a second edge (rightmost edge; Fig. 5B) of the metal interconnect feature.
(Re Claim 18) Modified Ponoth teaches the method of claim 16, but has not been shown explicitly to teach the etching process is performed into the second dielectric layer by at least 20% of the maximum thickness of the second dielectric layer between the lower surface of the third dielectric layer and the upper surface of the first dielectric layer.
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30)
As described in the rejection of claim 16, a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), and so a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form trenches in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each trench are result effective variables of the etch depth; the etch rate will be faster for wider trenches on the lowest level of Ponoth; the trenches used to form a second and third metal interconnect feature may be wider than most or all of the other trenches formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical etch depth into the second dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
(Re Claim 19) Modified Ponoth teaches the method of claim 16, but has not been shown explicitly to teach performing the etching process comprises: performing a first etching process using a first etching chemistry to remove portions of the fourth dielectric layer an expose the third dielectric; and performing a second etching process using a second etching chemistry that is different than the first etch chemistry to remove portions of the third dielectric layer and the second dielectric layer.
Ponoth performing an etching process (Fig. 3A-3C) comprises: performing a first etching process using a first etching chemistry (the selective etch of 311; ¶37) to remove portions of a fourth dielectric layer (311; Fig. 3C) to expose a third dielectric layer (310; Fig. 3C) at the bottom of the first trench and the second trench; and
performing a second etching process (“capping layer 310 at the bottom of 312b may be removed if it still remains”; ¶37) using a second etching chemistry (the nonselective etch of 310; ¶37) that is different from the first etch chemistry to remove portions of the third dielectric layer (“capping layer 310 at the bottom of 312b may be removed if it still remains” (¶37); “etch capping layer 310 as well and therefore may expose conductive stud 302” (¶36)).
A PHOSITA would find it obvious to etch through the fourth dielectric layer to expose the third dielectric layer of modified Ponoth using a first etching process, and then etch through the third dielectric layer using a second etching process as taught by Ponoth’s Fig. 3C embodiment, to allow for controlling the depths of metal features (¶¶29, 35).
Ponoth teaches that “trenches of different widths are preferably formed and sometimes required to be formed at approximately the same depth, therefore having the same contrast, in order for them to interact properly and/or function efficiently.” (¶29).
As is shown in Ponoth’s Fig. 5B, it would be obvious to continue the second etching process through the third dielectric and into the second dielectric such that portions of the second dielectric are removed, as overetching into the second dielectric for the trench ensures features smaller than the trench at the depth below Ponoth’s 520 have their corresponding portions of the third dielectric layer removed to allow for connections from within the second dielectric to be routed outside it. Smaller features etch slower than larger ones (Ponoth: Fig. 7, ¶¶44-45), and it is preferred for trenches of different sizes to be formed at any one depth.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276), Ruan et al. (US 2008/0150131), Drizlikh et al. (US 7,504,304), and Dunn et al. (US 2011/0091815) as applied to claim 19 above, and further in view of Worsham et al. (US 7,307,025).
(Re Claim 20) Modified Ponoth teaches the method of claim 19, but has not been shown explicitly to teach the second etching chemistry is selected based on a pattern density loading characteristic of the integrated circuit device.
Worsham teaches using a second etching chemistry (the lag and reverse lag etch cycle 112; Fig. 1) based on a pattern density loading characteristic of the integrated circuit device (col. 6 ln. 52-58).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize a second etching chemistry based on a pattern density loading characteristic of the integrated circuit device as claimed, to attain a uniform etch depth for all features that are intended to connect to other features beneath the third dielectric of modified Ponoth (Ponoth: “trenches of different widths are preferably formed and sometimes required to be formed at approximately the same depth, therefore having the same contrast, in order for them to interact properly and/or function efficiently“ (¶29)).
Conclusion
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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