DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 5-6, 9, 14-16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (US 20190043803).
Regarding claim 2, You teaches, in Fig. 11, a structure ([0010], [0017]), comprising:
a first conductive feature (110, [0029]) in a first dielectric layer (100, [0028]);
a plurality of second dielectric layers (201/202/203/300, [0042], [0045], AlN and AlOC are insulators) over the first conductive feature (110);
a conductive via (440, [0065]) in one or more dielectric layers of the plurality of second dielectric layers (201/202/203/300), the conductive via comprising:
a lower portion (441, [0061]) extending through a first subset (201/202) of the plurality of second dielectric layers (201/202/203/300); and
an upper portion (443, [0061]) over the lower portion (441) and extending through a second subset (203) of the plurality of second dielectric layers (201/202/203/300), wherein in a first cross-section a bottom surface of the upper portion (443) extends laterally from opposing sidewalls of the lower portion (441) (see Fig. 11); and
a conductive line (430, [0065]) on the conductive via (440), sidewalls of the conductive line (430) being covered by an upper layer (300) of the plurality of second dielectric layers (201/202/203/300).
Regarding claim 5, You further teaches, in Fig. 20, that sidewalls of the upper portion (443) are aligned with sidewalls of the lower portion (441) along a second cross-section ([0113], see Fig. 20 that is a cross-sectional view along line B-B' of Fig. 1), wherein the first cross-section ([0107], see Fig. 17 that is a cross-sectional view along A-A' of Fig. 1) is perpendicular to the second cross-section in a plan view (see Fig. 1).
Regarding claim 9, You teaches, in Fig. 17, a structure ([0010], [0020]), comprising:
a first conductive feature (110, [0029]) in a first dielectric layer (100, [0028]);
a plurality of second dielectric layers (201/202/203/300, [0042], [0045], AlN and AlOC are insulators) over the first dielectric layer (100);
a conductive line (430, [0065]) in an uppermost layer (300) of the plurality of second dielectric layers (201/202/203/300); and
a conductive via (440, [0065]) extending from the conductive line (430) to the first conductive feature (110), wherein the conductive via comprises a top via portion (443, [0061]) and a bottom via portion (441, [0061]), the top via portion (443) being adjacent the conductive line (430), the bottom via portion (441) being adjacent the first conductive feature (110), wherein a bottom surface of the top via portion (443) contacts at least one of the plurality of second dielectric layers (203) in a first cross-sectional view (see Fig. 17).
Regarding claim 14, You further teaches, in Fig. 17, that the plurality of second dielectric layers (201/202/203/300) comprises: a third dielectric layer (203) over the first dielectric layer (100); a fourth dielectric layer (202) on the third dielectric layer (203); and a fifth dielectric layer (300) on the fourth dielectric layer (202), wherein an upper surface of the conductive line (430) is level with an upper surface of the fifth dielectric layer (300) (see Fig. 17).
Regarding claim 15, You further teaches, in Fig. 17, that the bottom surface of the top via portion (443) contacts an upper surface of the third dielectric layer (203).
Regarding claim 16, You further teaches, in Fig. 17, that the plurality of second dielectric layers (201/202/203/300) further comprises: a sixth dielectric layer (201) between the third dielectric layer (203) and the first dielectric layer (100) (see Fig. 17).
Regarding claim 17, You teaches, in Figs. 17 and 20, a structure ([0010], [0020]), comprising:
a first conductive feature (110, [0029]) in a first dielectric layer (100, [0028]);
one or more second dielectric layers (201/202/203, [0042]) over the first dielectric layer (100);
one or more third dielectric layers (300, [0045]) over the one or more second dielectric layers (201/202/203);
a conductive line (430, [0065]) in a first upper dielectric layer (300) of the one or more third dielectric layers, wherein an upper surface of the conductive line (430) is level with an upper surface of the first upper dielectric layer (300) (see Fig. 17); and
a conductive via (440, [0065]) in the one or more second dielectric layers (201/202/203) and the one or more third dielectric layers (300), the conductive via comprising:
a lower portion (441, [0061]) extending through the one or more second dielectric layers (201/202/203); and
a upper portion (443, [0061]) extending through the one or more third dielectric layers (300), wherein a bottom surface of the upper portion (443) contacts an upper surface of the one or more second dielectric layers (201/202/203, upper surface of 203) in a first cross section ([0107], see Fig. 17 that is a cross-sectional view along A-A' of Fig. 1), wherein a sidewall of the upper portion (443) is aligned with a sidewall of the lower portion (441) at the upper surface of the one or more second dielectric layers (203) in a second cross section ([0113], see Fig. 20 that is a cross-sectional view along line B-B' of Fig. 1) (see below drawn plan view of via 440 that simultaneously incorporates Figs. 17 and 20).
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Plan view of You’s via 440 at top surface of layer 203 based on Figs. 17 and 20
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 6, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Kim et al. (US 20200051909).
Regarding claim 3, You teaches the limitations of claim 2. You does not teach a second conductive feature in the first dielectric layer, wherein the conductive via extends over the second conductive feature.
In a similar field of endeavor, Kim teaches, in Fig. 2, a second conductive feature (120, [0017]) in the first dielectric layer (100, [0019]), wherein the conductive via (150, [0016]) extends over the second conductive feature (120) (see Fig. 2), in order to decrease diffusion of conductive material from the via to the second conductive feature ([0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of You with the second conductive feature of Kim, in order to decrease diffusion of conductive material from the via to the second conductive feature ([0048]).
Regarding claim 6, You teaches the limitations of claim 2. You does not teach, in Fig. 11, that the bottom surface of the upper portion is on an upper surface of a third dielectric layer of the plurality of second dielectric layers.
In a similar field of endeavor, Kim teaches, in Fig. 5, that the bottom surface of the upper portion (of 150 in layers 142 and 143, [0038]) is on an upper surface of a third dielectric layer (141, [0043]) of the plurality of second dielectric layers (130/141, [0027], “the etching stop film 130 may include a plurality of layers” so 141 can be a third dielectric layer), in order to better prevent damage to the lower wiring ([0075]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of You with the third dielectric layer of Kim, in order to better prevent damage to the lower conductive feature ([0075]).
Regarding claim 18, You teaches the limitations of claim 17. You does not teach a second conductive feature in the first dielectric layer, wherein the conductive via extends over the second conductive feature.
In a similar field of endeavor, Kim teaches, in Fig. 2, a second conductive feature (120, [0017]) in the first dielectric layer (100, [0019]), wherein the conductive via (150, [0016]) extends over the second conductive feature (120) (see Fig. 2), in order to decrease diffusion of conductive material from the via to the second conductive feature ([0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of You with the second conductive feature of Kim, in order to decrease diffusion of conductive material from the via to the second conductive feature ([0048]).
Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Lu et al. (US 20130256902).
Regarding claim 4, You teaches the limitations of claim 2. You further teaches, in Fig. 17, that the lower portion (441) has a first width (W51) measured across a top of the lower portion, wherein the upper portion (443) has a second width (W61) measured across a bottom of the upper portion, wherein the second width is greater than the first width ([0108]).
You does not teach that the second width is greater than or equal to 1.4 times the first width.
In a similar field of endeavor, Lu teaches, in Fig. 3, that the second width (of 204, [0030]) is greater than or equal to 1.4 times the first width (of 202, [0020], [0029]) (the second width ranges from 100 to 200 nm while the first width ranges from 30-36 nm, so the second width is at least 100/36 = 2.7 times the first width), in order to provide reduced resistance, higher current, and faster charge conveyance ([0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the via width ratio of You with the via width ratio of Lu, in order to provide reduced resistance, higher current, and faster charge conveyance ([0030]).
Regarding claim 19, You teaches the limitations of claim 17. You further teaches, in Fig. 17, that a bottom of the upper portion (443) has a first width (W61), wherein a top of the lower portion (441) has a second width (W51), wherein the first width (W61) is greater than the second width (W51) ([0108]).
You does not teach that the first width is greater than or equal to 1.4 times the second width.
In a similar field of endeavor, Lu teaches, in Fig. 3, that the first width (of bottom of 204, [0030]) is greater than or equal to 1.4 times the second width (of top of 202, [0020], [0029]) (the first width ranges from 100 to 200 nm while the second width ranges from 30-36 nm, so the first width is at least 100/36 = 2.7 times the second width), in order to provide reduced resistance, higher current, and faster charge conveyance ([0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the via width ratio of You with the via width ratio of Lu, in order to provide reduced resistance, higher current, and faster charge conveyance ([0030]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Wang et al. (US 20190164887).
Regarding claim 7, You teaches the limitations of claim 2. You further teaches that the lower portion (441) contacts the first conductive feature (110) (see Fig. 17).
You does not teach that a width of the lower portion at an interface between the lower portion and the first conductive feature is in a range between 8 nm to 20 nm.
In a similar field of endeavor, Wang teaches that a width of the lower portion (Fig. 15, 60, [0035]) at an interface between the lower portion and the first conductive feature (24, [0035]) is in a range between 8 nm to 20 nm ([0059]), in order to scale down the device size and reduce the wire resistance ([0002], [0063]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the via widths of You with the via widths of Wang, in order to scale down the device size and reduce the wire resistance ([0002], [0063]).
Regarding claim 8, You in view of Wang teaches the limitations of claim 7. Wang further teaches that a width (W2, Fig. 2) of the upper portion (84, [0053]) at an interface between the upper portion and the lower portion (60) is in a range between 14 nm to 40 nm ([0025], 18-36 nm).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Chang et al. (US 20190148287).
Regarding claim 10, You teaches the limitations of claim 9. You does not teach that the bottom via portion has a thickness in a range of 25 Angstroms to 125 Angstroms.
In a similar field of endeavor, Chang teaches, in Fig. 12, that the bottom via portion (labelled as 216 in Fig. 2A, [0021]) has a thickness in a range of 25 Angstroms to 125 Angstroms ([0021], [0030], 5 nm because the bottom via portion has the same thickness as 406), in order to reduce the wire resistance ([0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bottom via portion thickness of You with the bottom via portion thickness of Chang, in order to reduce the wire resistance ([0040]).
Regarding claim 11, You teaches the limitations of claim 9. You does not teach that the top via portion has a thickness in a range of 275 Angstroms to 630 Angstroms.
In a similar field of endeavor, Chang teaches, in Fig. 2A, that the top via portion (214, [0022]) has a thickness in a range of 125 Angstroms to 1250 Angstroms ([0021], H1 ranges from 1-10 nm, and the height ratio of the bottom via portion to the top via portion can be 8%, so H2 can range from 12.5-125 nm), in order to reduce the wire resistance ([0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the top via portion thickness of You with the top via portion thickness of Chang, in order to reduce the wire resistance ([0040]).
However, You in view of Chang does not explicitly teach that the top via portion has a thickness in a range of 275 Angstroms to 630 Angstroms. Nonetheless, the skilled artisan would know too that the thickness of the top via portion would impact wire resistance (Chang, [0040]).
The specific claimed thicknesses, absent any criticality, is only considered to be the “optimum” thicknesses disclosed by You in view of Chang that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired wire resistances, device sizes, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the top via portion having a thickness in a range of 275 Angstroms to 630 Angstroms is used, as already suggested by You in view of Chang.
Since the applicant has not established the criticality (see next paragraph) of the thicknesses stated and since these thicknesses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of You in view of Chang.
Please note that the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 12, You teaches the limitations of claim 9. You does not teach that a top width of the top via portion is greater than or equal to 1.8 times a bottom width of the top via portion.
In a similar field of endeavor, Chang teaches, in Fig. 2A, that a top width (W3) of the top via portion (214, [0022]) is greater than or equal to 1.8 times a bottom width (W2) of the top via portion ([0023], 2.5 times), in order to “allow for electrical connection between interconnects of metal layers (or directly with the semiconductor devices in the substrate) with better contacts and less resistance” ([0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the top via portion widths of You with the top via portion widths of Chang, in order to allow for electrical connection between interconnects of metal layers (or directly with the semiconductor devices in the substrate) with better contacts and less resistance ([0019]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Tsai (US 20190067179).
Regarding claim 13, You teaches the limitations of claim 9. You does not teach that a top width of the bottom via portion is greater than or equal to 1.25 times a bottom width of the bottom via portion.
In a similar field of endeavor, Tsai teaches that a top width (W3, [0060], 64.1 nm) of the bottom via portion (605, [0060]) is greater than or equal to 1.25 times a bottom width (W4, 28.3 nm) of the bottom via portion (605) (see Fig. 10, [0060], 64.1/28.3 nm = 2.27 times), in order to prevent voids from forming during the via formation ([0059]-[0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bottom via widths of You with the bottom via widths of Tsai, in order to prevent voids from forming during the via formation ([0059]-[0060]).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20190043803) in view of Lu et al. (US 20130256902), and further in view of Chang et al. (US 20190148287).
Regarding claim 20, You in view of Lu teaches the limitations of claim 19. You in view of Lu does not teach that a top of the upper portion has a third width, the third width being greater than or equal to 1.8 times the first width.
In a similar field of endeavor, Chang teaches, in Fig. 2A, that a top width (W3) of the top via portion (214, [0022]) is greater than or equal to 1.8 times a bottom width (W2) of the top via portion ([0023], 2.5 times), in order to “allow for electrical connection between interconnects of metal layers (or directly with the semiconductor devices in the substrate) with better contacts and less resistance” ([0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the top via portion widths of You in view of Lu with the top via portion widths of Chang, in order to allow for electrical connection between interconnects of metal layers (or directly with the semiconductor devices in the substrate) with better contacts and less resistance ([0019]).
Regarding claim 21, You in view of Lu and Chang teaches the limitations of claim 20. Lu further teaches, in Fig. 3, that a bottom of the lower portion (202) has a fourth width (which is equal to the top of the 202), wherein the first width (of bottom of 204) is greater than or equal to 1.2 times the fourth width (the first width ranges from 100 to 200 nm, while the fourth width ranges from 30-36 nm, so the first width is at least 100/36 = 2.7 times the fourth width).
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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