DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8, 16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 20200303521A1) in view of Dories et al (US 20200066508A1).
Re claim 1 Son teaches a method comprising:
forming an opening (R1 , fig 16A) [0034] through a multilayer stack (104/NSS, fig16A) [0028/0107] and into a substrate (102) [0025];
depositing a first semiconductor material (132, fig 19A) [0035] in the opening (R1);
forming a second semiconductor material (134, fig 20A) [0042] over the first semiconductor material (132, P-type) [0036], the second semiconductor material (134, n-type) [0044] being differently doped (n-type doped) from the first semiconductor material (undoped 132) [0044];
forming a stack of nanostructures (NSS, fig 19A) [0117] by removing sacrificial layers (104, fig 20A) of the multilayer stack (104/NSS), the second semiconductor material (134, fig 20A) [0042] being electrically coupled to the stack of nanostructures (NSS, fig 20A); and
wherein the forming the second semiconductor material (134, fig 20A) [0044] comprises doping the second semiconductor material (134) with an n-type dopant [0044] and wherein the first semiconductor material (132,fig 20A) is not doped [0044].
Son does not teach forming channel interface structures at distal ends of the stack of nanostructure prior to forming the second semiconductor material.
Dories teaches forming channel interface structures (5b on each nanowire 40, fig 5, 14) [0033] at distal ends of the stack of nanostructure (40, fig 5, 14) [0056] prior to forming the second semiconductor material (35, fig 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Dories into the structure of Son to include forming channel interface structures at distal ends of the stack of nanostructure prior to forming the second semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son based on the teaching of Dories in the above manner for the purpose of reducing overlap capacitance, risk of shorting, and current leakage [0030].
Re claim 5 Son in view of Dories teach the method of claim 1, wherein forming the second semiconductor material (35, fig 9) [Dories, 0051] comprises forming the second semiconductor material (35, fig 9) [0051] in direct physical contact with the channel interface structures (5b, fig 9) [Dories, 0051].
Re claim 6 Son in view of Dories teach the method of claim 1, wherein depositing the first semiconductor material (132, fig 20A) [0035] comprises depositing the first semiconductor material (132, fig 20A) [0035] to a level (132B, fig 20A) that is higher than a top surface of the substrate (102, fig 20A) [0094].
Re claim 8 Son in view of Dories teach the method of claim 1, wherein a top surface of the first semiconductor material (132, fig 20A) [0036] is convex. (see fig 20A).
Re claim 16 Son teaches a method comprising:
forming a multilayer structure (104/NSS, fig 11) [0107] comprising alternating first semiconductor layers (104, fig 11) and second semiconductor layers (NSS, fig 11);
etching [0115] an opening (R1, fig 16A) [0115] in the multilayer structure (104/NSS, fig 11) , wherein the opening (R1, fig 16A) extends into a substrate (102,fig 16A) underlying the multilayer structure (fig16A);
forming a bottom structure (132, fig19A-20A) [0119] of a source/drain region (132/134, fig 20A) [0120] between along a bottom (bottom of R1) of the opening (R1)
forming a top structure (134, fig 20A) [0119] of the source/drain region (132/134, fig 20A) over the bottom structure (132, fig 20A) in the opening (R1), the top structure (134, fig 20A) having a higher dopant concentration (134 the dopant concentration of the portion far from 132 may be higher) [0045] than the bottom structure (132, fig 20A); and
replacing the first semiconductor layers (104, fig 26) with a gate structure (160, fig 26] [0127].
Son does not teach and forming a channel region interface structure along sidewalls of the second semiconductor layers of the multilayer structure in the opening;
Dories teaches forming a channel region interface structures (5b on each nanowire 40, fig 5, 14) [0033] along sidewall of the second semiconductor layers (40, fig 5, 14) [0056] of the multilayer structure in the opening (fig 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Dories into the structure of Son to include forming a channel region interface structure along sidewalls of the second semiconductor layers of the multilayer structure in the opening as claimed.
The ordinary artisan would have been motivated to modify Son based on the teaching of Dories in the above manner for the purpose of reducing overlap capacitance, risk of shorting, and current leakage [0030].
Re claim 19 Son in view of Dories teach the method of claim 16, wherein further comprising forming inner spacers(120, fig 18) [0048] on sidewalls of the first semiconductor layers (104, fig 18) [Son, 0107] prior to forming the bottom structure (132, fig 18) [Son, 0107].
Re claim 20 Son in view of Dories teach the method of claim 19, wherein forming the bottom structure (132, fig 20A) [Son, 0119] comprises forming the bottom structure (132, fig 20A) [0119] in direct physical contact with a sidewall of the inner spacers (120, fig 20A) [Son,0119].
Claims 2, 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Dories as applied to claims 1 and 16 and further in view of Chang et al (US20210273098A1).
Re claim 2 Son in view of Dories teach the method of claim 1,
Son and Dories do not teach the channel interface structures are formed simultaneously with the first semiconductor material.
Chang teaches the channel interface structures (92D, fig 38D) [0095] are formed simultaneously with the first semiconductor material (bottom 92D, fig 38D) [0095].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of Son and Dories to include the channel interface structures are formed simultaneously with the first semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Chang in the above manner for the purpose of improving device performance and reducing device defects [0091].
Re claim 7 Son in view of Dories teach the method of claim 1,
Son in view of Dories do not teach a height of the first semiconductor material is in a range between 3 nm and 30 nm.
Chang teaches teach a height of the first semiconductor material is in a range between 3 nm and 30 nm (bottom 92A, fig 38B) [0091].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of Son and Dories to include a height of the first semiconductor material is in a range between 3 nm and 30 nm as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Chang in the above manner for the purpose of improving device performance and reducing device defects [0091].
Re claim 17 Son in view Dories the method of claim 16,
Son and Dories do not teach the bottom structure and the channel region interface structure have a same material composition.
Chang teaches the bottom structure (bottom of 92D, fig 38B) and the channel region interface structure (upper 92D.fig 38B) have a same material composition (doped semiconductor material) [0095].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of Son and Dories to include the bottom structure and the channel region interface structure have a same material composition as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Chang in the above manner for the purpose of improving device performance and decrease device defects [0063].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Dories as applied to claim 1 and further in view of Ching et al (US20170047432A1).
Re claim 3 Son in view of Dories teach the method of claim 1 (fig 11-27A),
Son and Dories do not teach the channel interface structures are not doped prior to forming the second semiconductor material.
Ching teaches the channel interface structures (112, fig 1) [0047] are not doped prior to forming the second semiconductor material (120, fig 1) [0048].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ching into the structure of Son and Dories to include the channel interface structures are not doped prior to forming the second semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Ching in the above manner for the purpose of enhancing the device performance [0047].
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Dories as applied to claims 1 and 16 and further in view of Zang et al (US 9443931B2).
Re claim 4 Son in view of Dories teach the method of claim 1 further comprising
Son and Dories do not teach removing the channel interface structures prior to forming the second semiconductor material.
Zang does tech (Fig 3A-3B) comprising removing a channel interface structure (210) prior to forming the second semiconductor material (140) [38].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zang into the structure of Son and Dories to include removing the channel interface structures prior to forming the second semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Zang in the above manner for the purpose of achieving superior short-channel performance.
Re claim 18 Son in view of Dories teach the method of claim 16 further comprising
Son and Dories do not teach removing the channel region interface structure prior to forming the top structure of the source/drain region.
Zang does tech (Fig 3A-3B) removing the channel region interface structure (210) prior to forming the top structure of the source/drain region (140, fig 3A-3B)[38].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zang into the structure of Son and Dories to include removing the channel region interface structure prior to forming the top structure of the source/drain region as claimed.
The ordinary artisan would have been motivated to modify Son and Dories based on the teaching of Zang in the above manner for the purpose of achieving superior short-channel performance.
Claims 9, 12-13 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 20200303521A1) in view of Xu et al (US11011643B2).
Re claim 9 Son teaches a method comprising:
forming an opening (R1, fig 16A) [0034] through a multilayer stack (NS/104, fig 16A) [0034] and into a substrate (102, fig 16A) [0093], the multilayer stack (NS/104, fig 16A) [0034] comprising alternating sacrificial layers (104, fig 16A) [0107] and semiconductor layers (NSS, fig 16A), the opening (R1, fig 16A) exposing sidewalls of the sacrificial layers and the semiconductor layers (fig 20A);
depositing a first semiconductor material (132, fig 20A) [0035] in the opening (R1, fig 16A),
forming a second semiconductor material (134,fig 20A) [0042] over the first semiconductor material (132, fig 20A) ; and
forming a stack of nanostructures (NSS, fig 20A) by removing the sacrificial layers (104, fig 20A) of the multilayer stack (NSS/104, fig 20A), the second semiconductor material (134, fig 20A) being electrically coupled (184, fig 27A) to the stack of nanostructures (NSS, fig27),
Son does not explicitly teach first semiconductor material and the semiconductor layers have same conductivity type;
Xu does teach first semiconductor material (132) (69) and the semiconductor layers have (114) (56) have same conductivity type.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Xu into the structure of Son to include first semiconductor material and the semiconductor layers have same conductivity type as claimed.
The ordinary artisan would have been motivated to modify Xu based on the teaching of Son in the above manner for the purpose of it is essential while saving time and cost.
Son/Xu does not teach an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view.
Son different embodiment fig 7 teaches an uppermost surface (top of 632, fig 7) of the first semiconductor material (632, fig 7) [0071] is lower than a lower surface (lower side of N1) [0072] of a lowermost nanostructure (N1, fig 7) of the stack of nanostructures (NSS, fig 7) in a cross-sectional view (fig 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Son into the structure of Son/Xu to include an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view as claimed.
The ordinary artisan would have been motivated to modify Son/Xu based on the teaching of Son in the above manner for the purpose to decrease a leakage current and a junction capacitance [0052].
Re claim 12 Son in view of Xu teach the method of claim 9, wherein the uppermost surface of the first semiconductor material (upper surface of 132, fig 20A) [ Son, 0037] is higher than an upper most surface of the substrate (102, fig 20A) [Son, 0025].
Re claim 13 Son in view of Xu teach the method of claim 9, wherein a distance between the uppermost surface of the first semiconductor material (top of 632, fig 7) [0041] and the lower surface of the lowermost nanostructure (N1, fig 7) [0041] is in a range of 3nm to 20nm.[Son 0041].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Xu as applied to claim 10 and further in view of Dories et al (US 20200066508A1).
Re claim 10 Son in view of Xu teach the method of claim 9,
Son and Xu do not teach after forming the opening, forming channel interface structures are distal ends of the stack of nanostructures prior to forming the second semiconductor material.
Dories teaches forming channel interface structures (5b on each nanowire 40, fig 5, 14) [0033] at distal ends of the stack of nanostructure (40, fig 5, 14) [0056] prior to forming the second semiconductor material (35, fig 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Dories into the structure of Son and Xu to include forming channel interface structures at distal ends of the stack of nanostructure prior to forming the second semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son and Xu based on the teaching of Dories in the above manner for the purpose of reducing overlap capacitance, risk of shorting, and current leakage [0030].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Xu and Dories as applied to claim 1 and 10 further in view of Zang et al (US 9443931B2).
Re claim 11 Son in view of Xu and Dories teach the method of claim 1 further comprising
Son, Xu and Dories do not teach removing the channel interface structures prior to forming the second semiconductor material.
Zang does tech (Fig 3A-3B) comprising removing a channel interface structure (210) prior to forming the second semiconductor material (140) [38].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zang into the structure of Son, Xu and Dories to include removing the channel interface structures prior to forming the second semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Son, Xu and Dories based on the teaching of Zang in the above manner for the purpose of achieving superior short-channel performance.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Son as modified by Xu as applied to claim 9 further in view of More et al (US 20190148527A1).
Re claim 14 Son in view of Xu teach the method of claim 9,
Son and Xu do not teach a height of the first semiconductor material is in a range between 3 nm and 30 nm.
More teaches a height of the first semiconductor material (126, fig 4) [0041]is in a range between 3 nm and 30 nm (3nm to about 10nm) [0041].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by More into the structure of Son and Xu to include a height of the first semiconductor material is in a range between 3 nm and 30 nm as claimed.
The ordinary artisan would have been motivated to modify Son and Xu based on the teaching of More in the above manner for the purpose of improving the current efficiency of the resulting semiconductor structure.
“Where the general condition of a claim is disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation "in reAller, 220F.2d 454, 456, 105 USPQ 233 (CCPA 1955) (MPEP Chapter 2100- Section 2144.05-Optimization of Ranges.)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Son modified by Xu as applied by claim 9 and further in view of Chang et al (US20210273098A1).
Re claim 15 Son in view of Xu teach the method of claim 9,
Son and Xu do not teach forming the second semiconductor material comprises forming the second semiconductor material in physical contact with distal ends of the stack of nanostructures.
Chang teaches forming the second semiconductor material (92A, fig 38A) [0091] comprises forming the second semiconductor material (92A, fig 38A) [0091] in physical contact with distal ends (92D, fig 38A) [0095] of the stack of nanostructures (54A/B/C, fig 38A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of to include forming the second semiconductor material comprises forming the second semiconductor material in physical contact with distal ends of the stack of nanostructures as claimed.
The ordinary artisan would have been motivated to modify Son and Xu based on the teaching of Chang in the above manner for the purpose of improving device performance and decrease device defects [0046].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 9 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of (US12132118B2). Although the claims at issue are not identical, they are not patentably distinct from each other because they both claim and require similar steps/features: forming an opening through multilayer stack and into the substrate, the multilayer comprising alternating sacrificial layers and semiconductor layers and semiconductor layers, the opening exposing sidewalls of the sacrificial layers and the semiconductor layers;
depositing a first semiconductor material in the opening, wherein the first semiconductor material and the semiconductor layers have a same conductivity type;
forming a second semiconductor material over the first semiconductor material; and forming a stack of nanostructures by removing the sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the stack of nanostructures,
wherein an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view.
Current Application 18/786529
US patent US12132118B2)
Re claim 9
forming an opening through multilayer stack and into the substrate, the multilayer comprising alternating sacrificial layers and semiconductor layers and semiconductor layers, the opening exposing sidewalls of the sacrificial layers and the semiconductor layers;
Re claim 1
forming an opening through multilayer stack and into the substrate, the multilayer comprising alternating sacrificial layers and semiconductor layers and semiconductor layers, the opening exposing sidewalls of the sacrificial layers and the semiconductor layers;
depositing a first semiconductor material in the opening, wherein the first semiconductor material and the semiconductor layers have a same conductivity type;
depositing a first semiconductor material in the opening, wherein depositing the first semiconductor material comprises depositing a first portion along a bottom of the opening and a second portion on the sidewalls of the semiconductor layers, wherein the first semiconductor material and the semiconductor layers have a same conductivity type
forming a second semiconductor material over the first semiconductor material; and forming a stack of nanostructures by removing the sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the stack of nanostructures,
removing at least a portion of the second portion of the first semiconductor material:
forming a second semiconductor material over the first semiconductor material; and forming a stack of nanostructures by removing the sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the stack of nanostructures,
wherein an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view.
wherein an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view.
Conclusion
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 7/23/26
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