DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: “metal residue is comprises” should read, “metal residue comprises”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 2020/0043808 A1; hereafter Bao) in view of Wei et al. (US 2019/0096681 A1; hereafter Wei) and Hou et al. (US 2017/0170027 A1; hereafter Hou).
Regarding claim 1, Bao teaches a device (see e.g., semiconductor device 100, Figure 1) comprising:
a first nanostructure (see e.g., nanowire 108A, Para [0030], Figure 1);
a second nanostructure over the first nanostructure (see e.g., nanowire 108B over the nanowire 108A, Para [0030], Figure 1);
a first gate dielectric around the first nanostructure (see e.g., high-k dielectric material 110 wrapped around nanowire 108A, Para [0030], Figure 1);
a second gate dielectric around the second nanostructure (see e.g., high-k dielectric material 110 wrapped around nanowire 108B, Para [0030], Figure 1);
a gate electrode over the first gate dielectric and the second gate dielectric, wherein the gate electrode comprises a first work function metal; and (see e.g., a first work function metal 112 over the high-k dielectric material 110, Paras [0031], [0032], Figure 1)
Bao does not explicitly teach
“a first metal residue at an interface between the second gate dielectric and the first work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal”.
In a similar field of endeavor Wei teaches
a first metal residue at an interface between the second gate dielectric and the first work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. A thermal process drives fluorine from the dummy fluorine-containing layer 88 into the gate dielectric layer 82.
Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure. Residual tungsten remains between the gate dielectric layer 82 and the first work-function tuning layer 100.
The first work-function tuning layer 100 may comprise titanium nitride (TiN), titanium-silicon nitride, titanium-carbon nitride, titanium-aluminum nitride, tantalum nitride, tantalum-silicon nitride (TaSi.sub.xN.sub.y), tantalum-carbon nitride, cobalt, platinum. Accordingly, when the residual metal comprises tungsten and the first work-function tuning layer 100 comprises for example, a titanium-, tantalum-, cobalt or platinum material, the residual metal comprises a metal element different from the metal element of the first work function material, Paras [0034] - [0036], Figures 5-7).
Although Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of a first metal residue at an interface between the second gate dielectric and the first work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 2, Bao, as modified by Wei and Hou, teaches the limitations of claim 1 as mentioned above. Bao does not explicitly teach
“wherein the first gate dielectric and the second gate dielectric each comprise fluorine”.
In a similar field of endeavor Hou teaches performing fluorine treatment to drive fluorine into a high-k dielectric layer. Hou further explicitly teaches that the disclosed embodiments may also be applied to gate-all-around devices (see e.g., Para [0015]). In such an implementation, gate dielectric portions surrounding the respective nanostructures would have fluorine incorporated.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to incorporate fluorine in the first and second gate dielectric to obtain dielectric passivation and electrical performance benefits associated with fluorine incorporation.
Regarding claim 3, Bao, as modified by Wei and Hou, teaches the limitations of claim 2 as mentioned above. Bao further teaches
wherein the first gate dielectric further comprises hafnium oxide (see e.g., high-k dielectric material 110 includes hafnium oxide, Para [0034], Figure 1),
Bao does not explicitly teach
“wherein a ratio of fluorine to hafnium in the first gate dielectric is in a range of 0.015 to 0.4”.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In reAller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); MPEP § 2144.05.
In a similar field of endeavor Wei teaches fluorinating a high-k dielectric and explicitly teaches that the concentration of fluorine in the fluorinated gate dielectric may be greater than 0.5 percent of the gate dielectric layer 82, such as in a range from about 0.5 percent to about 9 percent.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize fluorine amount in the gate dielectric layer through routine experimentation to provide suitable fluorine concentration in the hafnium containing gate dielectric to obtain defect passivation and electrical performance benefits.
Regarding claim 4, Bao, as modified by Wei and Hou, teaches the limitations of claim 3 as mentioned above. Bao does not explicitly teach
“wherein a ratio of the metal element of the first metal residue to hafnium in a region between the first nanostructure and the second nanostructure is less than 0.1”.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In reAller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); MPEP § 2144.05.
In a similar field of endeavor Wei teaches performing a fluorination treatment using a fluorine- containing metal material, such as fluorine-doped tungsten, and further teaches that following removal of the fluorine-containing layer 88 residual metal, such as residual tungsten, may remain on the treated gate stack surface and remain detectable in the completed gate stack.
Although Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures. In such an implementation, any residual metal remaining would be present on the treated gate stack surfaces including the gate stack region between the first and second nanostructures.
The amount of residual metal remaining in the completed device would have been a result-effective parameter dependent on the fluorination and removal conditions.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize the amount of residual metal through routine experimentation to retain the desired fluorine induced dielectric passivation while minimizing unnecessary residual metal and thereby improve device performance. Optimizing the residual metal to hafnium in the region between the first and second nanostructures to a ratio of less than 0.1 would have been an obvious matter of routine optimization.
Regarding claim 5, Bao, as modified by Wei and Hou, teaches the limitations of claim 1 as mentioned above. Bao does not explicitly teach
“wherein the metal element of the first metal residue is tungsten”.
In a similar field of endeavor Wei teaches
wherein the metal element of the first metal residue is tungsten (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure, Para [0035])
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the metal element of the first metal residue is tungsten in the device of Bao to provide fluorine to the gate dielectric for dielectric passivation while utilizing a known fluorine-containing metal material.
Regarding claim 6, Bao, as modified by Wei, teaches the limitations of claim 1 as mentioned above. Bao does not explicitly teach
“further comprising a second metal residue at the interface between the second gate dielectric and the first work function metal, wherein the
second metal residue has a same metal element as the first metal residue, and wherein the second metal residue is disconnected from the first metal residue”.
In a similar field of endeavor Wei teaches performing a fluorination treatment using a fluorine- containing metal material, such as fluorine-doped tungsten, and further teaches that following removal of the fluorine-containing layer 88 residual metal, such as residual tungsten, may remain on the treated gate stack surface and remain detectable in the completed gate stack.
Although Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures. In such an implementation, any residual metal remaining on the surfaces treated would comprise the same metal element. Furthermore, because the residual metal remaining after removal of fluorine-containing layer 88 need not form a continuous metal film, discreet residual metal portions may remain at different locations across the treated gate stack surfaces. Accordingly, a first residual metal portion and a second residual metal portion would be physically disconnected from one another while comprising the same metal element.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement further comprising a second metal residue at the interface between the second gate dielectric and the first work function metal, wherein the second metal residue has a same metal element as the first metal residue, and wherein the second metal residue is disconnected from the first metal residue in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 7, Bao, as modified by Wei and Hou, teaches the limitations of claim 1 as mentioned above. Bao further teaches
wherein the gate electrode further comprises as a second work function metal (see e.g., second work-function metal 114, Para [0039], Figure 1),
Bao does not explicitly teach
“wherein the metal element of the first metal residue is different than a metal element of the second work function metal”.
In a similar field of endeavor Wei teaches
wherein the metal element of the first metal residue is different than a metal element of the second work function metal (see e.g., following removal of the fluorine-containing layer 88 residual metal, such as residual tungsten, may remain on the treated gate stack surface and remain detectable in the completed gate stack. The second work function tuning layer may comprise titanium aluminum carbide (TiAlC), a titanium aluminum alloy, tantalum-aluminum carbide. Accordingly, when the residual metal comprises tungsten and the second work function tuning layer 102 comprises for example, titanium aluminum-, tantalum aluminum-, the residual metal comprises a metal element different from the metal element of the second work function layer 102, Paras [0035], [0036], Figures 5-7)
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein the metal element of the first metal residue is different than a metal element of the second work function metal in the device of Bao in order to optimize work function tuning layer and improve overall device performance.
Regarding claim 8, Bao, as modified by Wei and Hou, teaches the limitations of claim 7 as mentioned above. Bao does not explicitly teach
“wherein the gate electrode further comprises:
an adhesion layer over the second work function metal; and
a fill metal over the adhesion layer”.
In a similar field of endeavor Wei teaches
wherein the gate electrode further comprises:
an adhesion layer over the second work function metal; and (see e.g., adhesion layer 104 conformally deposited on the second work function tuning layer 102, para [0037], Figure 7)
a fill metal over the adhesion layer (see e.g., metal gate electrode 106 over the adhesion layer 104, Para 0037], Figure 7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein the gate electrode further comprises: an adhesion layer over the second work function metal; and a fill metal over the adhesion layer in the device of Bao to form the gate electrode structure.
Regarding claim 9, Bao teaches a transistor (see e.g., semiconductor device 100, Figure 1) comprising:
a first nanostructure over a semiconductor substrate (see e.g., nanowire 108A on a semiconductor substrate 150, Para [0030], Figure 1);
a second nanostructure over the first nanostructure (see e.g., nanowire 108B over the nanowire 108A, Para [0030], Figure 1);
a gate dielectric surrounding the first nanostructure and the second nanostructure (see e.g., high-k dielectric material 110 wrapped around nanowires 108A and 108B, Para [0030], Figure 1),
wherein the gate dielectric comprises hafnium… (see e.g., high-k dielectric material 110 includes hafnium oxide, Para [0034], Figure 1);
and a gate electrode over the gate dielectric (see e.g., first work function metal 112 and second work function metal 114 disposed over the high-k gate dielectric materials 110, Para [0032], Figure 1),
wherein the gate electrode comprises:
a first p-type work function material (see e.g., the first work function metal 112 can be p-type work function metal layer for PFET, Para [0032], Figure 1);
a second p-type work function material over the first p-type work function material (see e.g., a second work function metal 114 over the first work function metal 112; both the first and second work function metals can be same type of material. Accordingly, if first work function metal 112 is p-type the second work function metal 114 will be p-type too, Para [0032], Figure 1);
Bao does not explicitly teach
“wherein the gate dielectric comprises hafnium and fluorine;
an adhesion layer over the second p-type work function material; and
a fill metal over the adhesion layer”.
Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures.
In a similar field of endeavor Wei teaches
wherein the gate dielectric comprises hafnium and fluorine (see e.g., the gate dielectric layer 82 includes hafnium, after the fluorination treatment fluorine diffuses into the gate dielectric layer 82, Para 0029], Figures 5-7), and
an adhesion layer over the second p-type work function material; and (see e.g., adhesion layer 104 over the second work-function tuning layer 102, Para [0037], Figure 7)
a fill metal over the adhesion layer (see e.g., metal gate electrode 106 over the adhesion layer 104, Para [0037], Figure 7),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the gate dielectric comprises hafnium and fluorine; an adhesion layer over the second p-type work function material; and a fill metal over the adhesion layer in the device of Bao to form a gate electrode structure.
Bao does not explicitly teach
“wherein a ratio of the fluorine to hafnium in the gate dielectric is in a range of 0.015 and 0.4;
wherein a peak concentration of fluorine is disposed at an interface between the gate dielectric and the first p-type work function material.”
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In reAller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); MPEP § 2144.05.
In a similar field of endeavor Wei teaches fluorinating a high-k dielectric and explicitly teaches that the concentration of fluorine in the fluorinated gate dielectric may be greater than 0.5 percent of the gate dielectric layer 82, such as in a range from about 0.5 percent to about 9 percent.
As illustrated by fluorine profiles 200, 202 and 204 of Figure 11, Wei teaches that the fluorine concentration within gate dielectric layer 82 has a concentration gradient. The fluorine concentration is greatest near the outer surface of gate dielectric layer 82 and decreases through the gate dielectric toward interfacial layer 80.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to incorporate and optimize the concentration fluorine in the gate dielectric such that a ratio of the fluorine to hafnium in the gate dielectric is in a range of 0.015 and 0.4 and a peak concentration of fluorine is disposed at an interface between the gate dielectric and the first p-type work function material in order to provide sufficient fluorine for passivation of defects in the high-k dielectric layer while maintaining desirable electrical characteristics and device performance. Such optimization of fluorine concentration and profile would have involved no more than routine experimentation of a known result effective parameter.
Regarding claim 10, Bao, as modified by Wei and Hou, teaches the limitations of claim 9 as mentioned above. Bao does not explicitly teach
“further comprising a metal residue at the interface between the gate dielectric and the first p-type work function material”.
In a similar field of endeavor Wei teaches
further comprising a metal residue at the interface between the gate dielectric and the first p-type work function material (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. A thermal process drives fluorine from the dummy fluorine-containing layer 88 into the gate dielectric layer 82.
Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure. Residual tungsten remains between the gate dielectric layer 82 and the first work-function tuning layer 100, Paras [0034] - [0036], Figures 5-7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of further comprising a metal residue at the interface between the gate dielectric and the first p-type work function material in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 11, Bao, as modified by Wei and Hou, teaches the limitations of claim 10 as mentioned above. Bao does not explicitly teach
“wherein the metal residue is comprises a metal other than the gate dielectric and other than the first p-type work function material”.
In a similar field of endeavor Wei teaches
wherein the metal residue is comprises a metal other than the gate dielectric and other than the first p-type work function material (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure.
The gate dielectric 82 comprises Hf, Al, Zr, La, Mg, Ba, Ti, Pb or a combination thereof.
The first work-function tuning layer 100 may comprise titanium nitride (TiN), titanium-silicon nitride, titanium-carbon nitride, titanium-aluminum nitride, tantalum nitride, tantalum-silicon nitride (TaSi.sub.xN.sub.y), tantalum-carbon nitride, cobalt, platinum.
Accordingly, when the residual metal comprises tungsten and, the gate dielectric comprises Hf, Al, Zr, La, Mg, Ba, Ti, Pb and first work-function tuning layer 100 comprises for example, a titanium-, tantalum-, cobalt or platinum material, the residual metal comprises a metal element different from the metal element of the gate dielectric and the first work function material, Paras [0034] - [0036], Figures 5-7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the metal residue is comprises a metal other than the gate dielectric and other than the first p-type work function material in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 12, Bao, as modified by Wei and Hou, teaches the limitations of claim 10 as mentioned above. Bao does not explicitly teach
“wherein the metal residue is tungsten”.
In a similar field of endeavor Wei teaches
wherein the metal residue is tungsten (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure, Para [0035])
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the metal residue is tungsten in the device of Bao to provide fluorine to the gate dielectric for dielectric passivation while utilizing a known fluorine-containing metal material.
Regarding claim 13, Bao, as modified by Wei and Hou, teaches the limitations of claim 9 as mentioned above. Bao does not explicitly teach
“wherein the first p-type work function material comprises fluorine, and wherein the fluorine in the first p-type work function material is primarily interstitially located in a film of the first p-type work function material”.
In a similar field of endeavor Wei teaches
wherein the first p-type work function material comprises fluorine, and wherein the fluorine in the first p-type work function material is primarily interstitially located in a film of the first p-type work function material (see e.g., first work-function tuning layer 100 may have an insubstantial amount of fluorine resulting, e.g., from natural diffusion or occurrence of fluorine independent of any processing, Para [0046], Figures 5-7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein the first p-type work function material comprises fluorine, and wherein the fluorine in the first p-type work function material is primarily interstitially located in a film of the first p-type work function material in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 14, Bao teaches a device (see e.g., semiconductor device 100, Figure 1) comprising:
a gate dielectric around a first semiconductor structure (see e.g., high-k dielectric material 110 wrapped around nanowire 108A, Para [0030], Figure 1),
a gate electrode over the gate dielectric, wherein the gate electrode comprises a first work function metal; and (see e.g., first work function metal 112 and second work function metal 114 disposed over the high-k gate dielectric materials 110, Para [0032], Figure 1)
Bao does not explicitly teach
“wherein the gate dielectric comprises fluorine;
discrete pockets of metal residue at an interface between the gate dielectric and the first work function metal, wherein the discrete pockets of metal residue are made of a first metal element that is different from a second metal element of the first work function metal”.
Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures.
In a similar field of endeavor Wei teaches
wherein the gate dielectric comprises fluorine (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. A thermal process drives fluorine from the dummy fluorine-containing layer 88 into the gate dielectric layer 82, Para 0029], Figures 5-7);
discrete pockets of metal residue at an interface between the gate dielectric and the first work function metal (see e.g., Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure. Residual tungsten remains between the gate dielectric layer 82 and the first work-function tuning layer 100. The remaining tungsten constitutes remnant portions of the removed tungsten containing material rather than the intentionally retained continuous fluorine containing layer, Paras [0034] - [0036], Figures 5-7), wherein the discrete pockets of metal residue are made of a first metal element that is different from a second metal element of the first work function metal (see e.g.,
The first work-function tuning layer 100 may comprise titanium nitride (TiN), titanium-silicon nitride, titanium-carbon nitride, titanium-aluminum nitride, tantalum nitride, tantalum-silicon nitride (TaSi.sub.xN.sub.y), tantalum-carbon nitride, cobalt, platinum.
Accordingly, when the residual metal comprises tungsten and the first work-function tuning layer 100 comprises for example, a titanium-, tantalum-, cobalt or platinum material, the residual metal comprises a metal element different from the metal element of the first work function material, Paras [0034] - [0036], Figures 5-7).
Therefore, it would have been obvious too ne skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the gate dielectric comprises fluorine; discrete pockets of metal residue at an interface between the gate dielectric and the first work function metal, wherein the discrete pockets of metal residue are made of a first metal element that is different from a second metal element of the first work function metal in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 15, Bao, as modified by Wei and Huo, teaches the limitations of claim 14 as mentioned above. Bao does not explicitly teach
“wherein the first metal element is tungsten”.
In a similar field of endeavor Wei teaches
wherein the first metal element is tungsten (see e.g., gate dielectric layer 82 is fluorinated using a dummy fluorine-containing layer 88 such as fluorine-doped tungsten. Following the removal of the dummy fluorine-containing layer 88, residual tungsten may remain on the treated surface and may remain detectable in the completed gate structure, Para [0035])
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wei’s teachings of wherein the first metal element is tungsten in the device of Bao to provide fluorine to the gate dielectric for dielectric passivation while utilizing a known fluorine-containing metal material.
Regarding claim 16, Bao, as modified by Wei and Huo, teaches the limitations of claim 14 as mentioned above. Bao does not explicitly teach
“wherein the gate dielectric further comprises a third metal element different from the first metal element”.
In a similar field of endeavor Wei teaches
wherein the gate dielectric further comprises a third metal element different from the first metal element (see e.g., The gate dielectric 82 comprises Hf, Al, Zr, La, Mg, Ba, Ti, Pb or a combination thereof.
Accordingly, when the residual metal comprises tungsten and the gate dielectric comprises Hf, Al, Zr, La, Mg, Ba, Ti, Pb, the residual metal comprises a metal element different from the metal element of the gate dielectric, Paras [0034] - [0036], Figures 5-7)
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein the gate dielectric further comprises a third metal element different from the first metal element in the device of Bao in order to optimize and improve overall device performance.
Regarding claim 17, Bao, as modified by Wei and Huo, teaches the limitations of claim 16 as mentioned above. Bao further teaches
further comprising a second semiconductor structure over the first semiconductor structure (see e.g., nanowire 108B over the nanowire 108A, Para [0030], Figure 1),
Bao does not explicitly teach
“wherein a ratio of the first metal element to the third metal element in a region between the first semiconductor structure and the second semiconductor structure is less than 0.1”.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In reAller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); MPEP § 2144.05.
In a similar field of endeavor Wei teaches performing a fluorination treatment using a fluorine- containing metal material, such as fluorine-doped tungsten, and further teaches that following removal of the fluorine-containing layer 88 residual metal, such as residual tungsten, may remain on the treated gate stack surface and remain detectable in the completed gate stack.
Although Wei illustrates this fluorination treatment in a non-gate-all-around transistor structure, Hou teaches that similar fluorination treatment may also be applied to gate-all-around transistor structures. In such an implementation, any residual metal remaining would be present on the treated gate stack surfaces including the gate stack region between the first and second nanostructures.
The amount of residual metal remaining in the completed device would have been a result-effective parameter dependent on the fluorination and removal conditions.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize the amount of residual metal through routine experimentation to retain the desired fluorine induced dielectric passivation while minimizing unnecessary residual metal and thereby improve device performance. Optimizing the residual metal to hafnium in the region between the first and second nanostructures to a ratio of less than 0.1 would have been an obvious matter of routine optimization.
Regarding claim 18, Bao, as modified by Wei and Huo, teaches the limitations of claim 16 as mentioned above. Bao does not explicitly teach
“wherein a ratio of the fluorine to the third metal element in the gate dielectric is in a range of 0.015 and 0.4”.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In reAller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); MPEP § 2144.05.
In a similar field of endeavor Wei teaches fluorinating a high-k dielectric and explicitly teaches that the concentration of fluorine in the fluorinated gate dielectric may be greater than 0.5 percent of the gate dielectric layer 82, such as in a range from about 0.5 percent to about 9 percent.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize fluorine amount in the gate dielectric layer through routine experimentation to provide suitable fluorine concentration in the hafnium containing gate dielectric to obtain defect passivation and electrical performance benefits.
Regarding claim 19, Bao, as modified by Wei, teaches the limitations of claim 14 as mentioned above. Bao does not explicitly teach
“wherein the first work function metal comprises fluorine”.
In a similar field of endeavor Wei teaches
wherein the first work function metal comprises fluorine (see e.g., first work-function tuning layer 100 may have an insubstantial amount of fluorine resulting, e.g., from natural diffusion or occurrence of fluorine independent of any processing, Para [0046], Figures 5-7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein the first work function metal comprises fluorine in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Regarding claim 20, Bao, as modified by Wei, teaches the limitations of claim 19 as mentioned above. Bao does not explicitly teach
“wherein a majority of fluorine in the first work function metal is interstitial”.
In a similar field of endeavor Wei teaches
wherein a majority of fluorine in the first work function metal is interstitial (see e.g., first work-function tuning layer 100 may have an insubstantial amount of fluorine resulting, e.g., from natural diffusion or occurrence of fluorine independent of any processing, Para [0046], Figures 5-7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Wei’s teachings of wherein a majority of fluorine in the first work function metal is interstitial in the device of Bao in order to optimize work-function tuning layer and improve overall device performance.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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