DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 13 objected to because of the following informalities: line 1 of claim 13 includes the phrase, “the s method of claim 12,” which includes a grammatical error. For the purpose of this office action, this phrase is interpreted to have the following meaning: the method of claim 12. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6, 8-9, and 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 10 and 12-15 are rejected as they include the limitations of claim 9 on which they depend.
Claim 4 recites the limitation, "wherein a portion of the underfill to reveal the ground plane before forming the heat dissipating structure," in lines 1-2 of the claim. The meets and bounds of this limitation are unclear, as it is unclear what action is performed on the underfill before forming the heat dissipating structure.
Claim 5 recites the limitation, "wherein a portion of the underfill to penetrate through the ground plane before forming the heat dissipating structure," in lines 1-2 of the claim. The meets and bounds of this limitation are unclear, as it is unclear what action is performed on the underfill before forming the heat dissipating structure.
Claim 6 recites the limitation, “the thermal relaxation block," in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. Furthermore, the meets and bounds of this limitation are unclear, as it is unclear whether this limitation is meant to be, “a thermal relaxation block,” or if the claim is meant to depend from claim 3 which introduces, “a thermal relaxation block”. For the purpose of this office action, claim 6 is interpreted to have the following meaning: the method of claim 3 further comprising: forming an electrically conductive adhesion layer between the thermal relaxation block and the ground plane.
Claim 8 recites the limitation, "wherein a portion of the underfill to reveal the electrically conductive ball before forming the heat dissipating structure," in lines 1-2 of the claim. The meets and bounds of this limitation are unclear, as it is unclear what action is performed on the underfill before forming the heat dissipating structure.
Claim 9 recites the limitation, "on the semiconductor die encapsulated by the encapsulant," in lines 2-3 of the claim. There is insufficient antecedent basis for “the semiconductor die“ and “the encapsulant” in this limitation in the claim. Claim 9 also recites the limitation, " between the first encapsulated chip and the second encapsulated chip," in lines 12-13 of the claim. There is insufficient antecedent basis for “the first encapsulated chip “ and “the second encapsulated chip” in this limitation in the claim.
Claim 11 recites the limitation, "forming a second redistribution structure on an active surface of the semiconductor die," in line 2 of the claim. The meets and bounds of this limitation are unclear, as it is unclear whether the second redistribution structure is formed on an active surface of the semiconductor die introduced in line 2 of independent claim 9 as, “the semiconductor die,” or whether the second redistribution structure is formed on an active surface of the semiconductor die introduced in line 5 of independent claim 9 as, “a semiconductor die”. The meets and bounds of this limitation of claim 11 are unclear, as it is unclear which semiconductor die the second redistribution structure is formed on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2-3, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US PGPub 20180197821 A1; hereinafter referred to as "Shin” in view of Hsu et al. (US PGPub 20190096866 A1; hereinafter referred to as "Hsu”).
Re claim 1: Shin teaches a manufacturing method of a semiconductor package, comprising: providing a bottom package having a redistribution structure and a semiconductor die connected to the redistribution structure (FIG. 3: el. (308, 304), 334, 302; para. 35| bottom package formed of substrate 308 having conductive traces 302 including a redistribution layer (RDL); bottom package also formed of an encapsulant 304 and a semiconductor die 334 connected to the substrate 308), wherein the redistribution structure comprises a ground plane (annotated FIG. 9; para. 54|conductive trace 302 includes a ground plane, labelled in annotated FIG. 9, provided below); connecting a top package to the redistribution structure of the bottom package (FIG. 3: el. (322, 324); para. 35); forming an encapsulant between the top package and the bottom package, wherein the encapsulant covers the ground plane (FIG. 3: el. 306; para. 35); and forming a heat dissipating structure penetrating through the encapsulant (FIG. 4A-4B: el. 402; para. 38-39| internal shield 402 formed of metal materials which are good conductors of both electricity and heat, and as such, the structure 402 can perform the function of dissipating heat), wherein the heat dissipating structure is in contact with the ground plane (annotated FIG. 9: el. 402, ground plane; para. 54| heat dissipating structure 402 in contact with ground plane of the conductive traces 302). Shin teaches that the top package may be electrically connected to the redistribution structure of the bottom package but fails to directly disclose that the semiconductor die and the top package are electrically connected to the redistribution structure. Shin also fails to directly disclose that the encapsulant between the top package and the bottom package is an underfill.
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In a similar field of endeavor, Hsu teaches a redistribution structure between a semiconductor die and a top sub-package of a semiconductor package (FIG. 1G: el. 150, 120, (210, 160); para. 17, 21). Hsu teaches a semiconductor die electrically connected to a redistribution structure and electrically connecting a top package to a redistribution structure (FIG. 1G: el. 150, 120, (210, 160); para. 17, 21 |redistribution structure 150 electrically connected to semiconductor die 120 and electrically connected to top sub-package components including chip 210 and conductive features 160). Hsu also teaches forming an encapsulant between the top package components and the bottom package components as an underfill that underfills the area between interconnects 160 of chip 210 (FIG. 1F: el. 220; para. 23). Hsu teaches forming an underfill between the top package and the bottom package (FIG. 1F: el. 220; para. 23). Hsu also teaches a benefit of electrically connecting the semiconductor die and top package components to the redistribution layer is to redistribute the conductive traces of the die and package components to enable transmitting signals to the semiconductor die and a benefit of forming the encapsulant as an underfill is the encapsulation of soldered interconnects (para. 17, para. 21-23).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Shin and Hsu, to enable using the underfill and electrically connectivity of package parts of Hsu in the manufacturing method of a semiconductor package of Shin, for the benefit of enabling signals to be transmitted between the semiconductor die and other package parts and the benefit of improving reliability by isolating neighboring interconnects.
Re claim 2: The combination of Shin and Hsu teaches the method of claim 1 further comprising forming a heat dissipating structure over the top package (Shin – FIG. 5: el. 502; para. 41| external shield 502 formed over the top package and formed of metal materials which are good conductors of both electricity and heat, and as such, the structure 502 can perform the function of dissipating heat).
Re claim 3: The combination of Shin and Hsu teaches the method of claim 1, wherein the heat dissipating structure comprises a thermal relaxation block, and the thermal relaxation block physically contacts the ground plane (Shin – annotated FIG. 9: el. 402, ground plane; para. 38-39, 54 |internal shield 402 formed of metal materials which are good conductors of both electricity and heat, and as such, the structure 402 can perform the function of thermal relaxation; thermal relaxation block 402 is grounded by contacting a ground portion, the ground plane, of conductive trace 302; ground plane of conductive trace 302 labelled in annotated FIG. 9, provided below).
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Re claim 7: The combination of Shin and Hsu teaches the method of claim 1 further comprising: forming an electrically conductive ball before forming the underfill (Hsu – FIG. 1D-1F: el. 160, 22| electrically conductive ball 160 formed before forming the underfill 220 to enable the electrical ball 160 to form electrical connections).
Claims 9, 12-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 9818722 B1; hereinafter referred to as "Wang”) in view of Erickson et al. (“New application method for package level EMI shield coating,” pg. 1-3; hereinafter referred to as “Erickson”).
Re claim 9: Wang teaches a manufacturing method of a semiconductor package, comprising: forming a first redistribution structure on the semiconductor die encapsulated by the encapsulant (FIG. 10: el. 150, 130, 135; para. 23| 1st redistribution structure 150 formed on semiconductor die 130 encapsulated by encapsulant 135; this semiconductor die 130 can be considered as the rightmost semiconductor die 130 of FIG. 10), wherein the first redistribution structure includes a ground plane and conductive layers (FIG. 10, annotated FIG. 26: el. 150; para. 23-24, 40| 1st redistribution structure includes 2 conductive layers and teaches that the exposed conductive plane of the redistribution layer is a grounded plane (para. 40); annotated FIG. 26, provided below labels the exposed portion of the redistribution layer 150 which is the grounded plane); providing a semiconductor die on the first redistribution structure and laterally encapsulating the semiconductor die with an encapsulant (FIG. 10: el. 150, 130, 135; para. 20, 23| a semiconductor die 130 is encapsulated with encapsulant 135 and provided on the 1st redistribution structure; this semiconductor die 130 can be considered as the leftmost semiconductor die 130 of FIG. 10); providing chips on the first redistribution structure and electrically connecting the chips to the conductive layers of the first redistribution structure (FIG. 11: el. 200; para. 25| chips 200 are electrically connected to the redistribution structure 150 by solder balls 210), wherein the chips and the semiconductor dies are disposed at opposite sides of the first redistribution structure (FIG. 11: el. 200, 150, 130); applying a thermally conductive material on the first redistribution structure to form a thermally conductive block disposed on the first redistribution structure as well as between the first encapsulated chip and the second encapsulated chip (annotated FIG. 26: el. 600; para. 37, 40| a metal coating, which is a thermally conductive material, is applied on an exposed portion of the redistribution layer 150 between the leftmost first encapsulated chip 200 and the rightmost encapsulated chip 200 of FIG. 26), wherein the thermally conductive block is electrically connected with the ground plane (annotated FIG. 26: el. thermally conductive block, ground plane| a portion of the metal coating 600 is considered as the thermally conductive block and is electrically connected with the grounded feature of the redistribution layer, the ground plane, so that the thermally conductive block is grounded). Wang also teaches applying the thermally conductive metal coating by spraying, but fails to disclose curing the thermally conductive material to form the thermally conductive block.
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In a similar field of endeavor, Erickson teaches a method of spraying thin conductive films on package parts to produce uniform thin conductive films with a reduced cost (pg. 1: abstract). Erickson teaches forming conductive films on package parts by spraying a conductive material and curing the conductive material to form the conductive film (pg. 2: FIG. 5; pg. 1: abstract, pg. 2: second to last paragraph). The combination of Wang and Erickson teaches curing the thermally conductive material to form the thermally conductive block (Erickson - pg. 2: FIG. 5; pg. 2: second to last paragraph). Erickson further teaches a benefit of the spray coating method which incorporates both a spray application step and a curing step is a reduction in the cost of applying conductive films to package parts (Erickson - pg. 1: abstract).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Wang and Erickson, to enable using the curing step of Erickson in the semiconductor package manufacturing method of Wang, for the benefit of simplifying manufacturing by using a known process for forming a metal film using a spray application method and the benefit of reduced cost.
Re claim 12: The combination of Wang and Erickson teaches the method of claim 9 further comprising: forming a thermally conductive cover layer, wherein the thermally conductive cover layer is disposed on the thermally conductive block and covers the chips (Wang - annotated FIG. 26: el. thermally conductive cover layer| annotated FIG. 26, provided below, labels the thermally conductive cover layer which is disposed on the thermally conductive block and covers the chips 200).
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Re claim 13: The combination of Wang and Erickson teaches the method of claim 12, wherein the thermally conductive cover layer comprises a cap portion disposed over and covering top surfaces of the first and second encapsulated chips, and the thermally conductive block and the cap portion are made of the same thermally conductive material (Wang - annotated FIG. 26: el. thermally conductive cover layer, thermally conductive cap; para. 37, 40| annotated FIG. 26, provided in Re claim 12 section, labels the thermally conductive cap of the thermally conductive cover layer; the cap portion is disposed over the 1st and 2nd encapsulated chips 200 and is made of the same thermally conductive material as the thermally conductive block, as the thermally conductive cap portion and the thermally conductive block are formed in the same deposition step).
Re claim 16: Wang teaches a manufacturing method of a semiconductor package, comprising: providing a semiconductor die (FIG. 7: el. 130; para. 18); forming a first redistribution structure disposed on the semiconductor die (FIG. 10: el. 150, 130; para. 23| 1st redistribution structure 150 formed on semiconductor die 130), wherein the first redistribution structure includes a ground plane and conductive layers (FIG. 10, annotated FIG. 26: el. 150; para. 23-24, 40| 1st redistribution structure includes 2 conductive layers and teaches that the exposed conductive plane of the redistribution layer is a grounded plane (para. 40); annotated FIG. 26, provided in Re claim 1 section, labels the exposed portion of the redistribution layer 150 which is the grounded plane); connecting a first encapsulated chip and a second encapsulated chip to the first redistribution structure (FIG. 11-12: el. 200; para. 25| 1st encapsulated chip (considered as leftmost encapsulated chip 200 of FIGs. 11 and 12) and 2nd encapsulated chip (considered as rightmost encapsulated chip 200 of FIGs. 11 and 12) are electrically connected to the redistribution structure 150 by solder balls 210), wherein the first and second encapsulated chips are arranged side by side (FIG. 11), the semiconductor die is spaced apart from the first encapsulated chip and the second encapsulated chip by the first redistribution structure (FIG. 11: el. 200, 150, 130), and the first and second encapsulated chips are electrically connected with the semiconductor die through the conductive layers of the first redistribution structure (FIG. 11, 10: el. 200, 130, 210, 150; para. 23, 25| 1st and 2nd semiconductor chips 200 are electrically connected with the semiconductor die 130 through the redistribution layer 150 and the solder balls 210 of the semiconductor chips 200); applying a thermally conductive material on the first redistribution structure to form a thermally conductive block disposed on the first redistribution structure as well as between the first encapsulated chip and the second encapsulated chip (FIG. 26: el. 600; para. 37, 40| a metal coating, which is a thermally conductive material, is applied on an exposed portion of the redistribution layer 150 between the leftmost first encapsulated chip 200 and the rightmost encapsulated chip 200 of FIG. 26), wherein the thermally conductive block is electrically connected with the ground plane (annotated FIG. 26: el. thermally conductive block, ground plane| a portion of the metal coating 600 is considered as the thermally conductive block and is electrically connected with the grounded feature of the redistribution layer, the ground plane, so that the thermally conductive block is grounded; annotated FIG. 26, provided in Re claim 1 section, labels the thermally conductive block). Wang also teaches applying the thermally conductive metal coating by spraying, but fails to disclose curing the thermally conductive material to form the thermally conductive block.
In a similar field of endeavor, Erickson teaches a method of spraying thin conductive films on package parts to produce uniform thin conductive films with a reduced cost (pg. 1: abstract). Erickson teaches forming conductive films on package parts by spraying a conductive material and curing the conductive material to form the conductive film (pg. 2: FIG. 5; pg. 1: abstract, pg. 2: second to last paragraph). The combination of Wang and Erickson teaches curing the thermally conductive material to form the thermally conductive block (Erickson - pg. 2: FIG. 5; pg. 2: second to last paragraph). Erickson further teaches a benefit of the spray coating method which incorporates both a spray application step and a curing step is a reduction in the cost of applying conductive films to package parts (Erickson - pg. 1: abstract).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Wang and Erickson, to enable using the curing step of Erickson in the semiconductor package manufacturing method of Wang, for the benefit of simplifying manufacturing by using a known process for forming a metal film using a spray application method and the benefit of reduced cost.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Erickson as applied to claim 12 above, and further in view of Craig (US PGPub 20170290209 A1; hereinafter referred to as "Craig”).
Re claim 14: The combination of Wang and Erickson fails to teach the method of claim 12 further comprising: providing a heat spreader on the cap portion of the thermally conductive cover layer.
In a similar field of endeavor, Craig teaches a semiconductor package formed with a lid which functions as both an EMI shield and a heat dissipating structure (FIG. 1: el. 114; para. 21) and a finned heat spreader (FIG. 1: el. 112; para. 21) formed on the lid (FIG. 1: el. 112, 114). Craig teaches providing a heat spreader (FIG. 1: el. 112; para. 21) on the cap portion (FIG. 1: el. 114; para. 21) of the thermally conductive cover layer (FIG. 1: el. (114, 116); para. 21). Craig further teaches a benefit of the finned heat spreader on the thermally conductive cover layer is the removal of package heat by providing a structure for radiating heat into the surrounding environment (para. 24).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Wang and Erickson with the teachings of Craig, to enable using heat spreader of Craig in the manufacturing method of a semiconductor package of the combination of Wang and Erickson, for the benefit of the removal of package heat by providing a structure for efficiently radiating heat into the surrounding environment.
Allowable Subject Matter
Claims 6, 10-11, 15, and 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 6: The closest prior art, Shin’821 and Hsu’866, either alone or in combination fails to disclose or suggest, “the method of claim 3 further comprising: forming an electrically conductive adhesion layer between the thermal relaxation block and the ground plane,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 10: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive adhesion layer, wherein the thermally conductive block is disposed on the electrically conductive adhesion layer,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 11: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming a second redistribution structure on an active surface of the semiconductor die, and conductive structures electrically connecting the second redistribution structure and the first redistribution structure,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 15: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive ball disposed between the thermally conductive block and the ground plane before forming the thermally conductive block,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 17: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive adhesion layer over the underfill and conformally covering sidewalls of the opening before applying the thermally conductive material,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 18: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive adhesion layer over the underfill and conformally covering sidewalls of the opening before applying the thermally conductive material,” of claim 17 on which claim 18 depends in combination with the additionally claimed features, as claimed by the applicant.
Re claim 19: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive adhesion layer over the underfill and conformally covering sidewalls of the opening before applying the thermally conductive material,” of claim 17 on which claim 19 depends in combination with the additionally claimed features, as claimed by the applicant.
Re claim 20: The closest prior art, Wang’722 and Erickson, either alone or in combination fails to disclose or suggest, “forming an electrically conductive adhesion layer over the underfill and conformally covering sidewalls of the opening before applying the thermally conductive material,” of claim 17 on which claim 20 depends in combination with the additionally claimed features, as claimed by the applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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