Prosecution Insights
Last updated: October 02, 2026
Application No. 18/786,587

SEMICONDUCTOR PACKAGE MODULE AND MANUFACTURING METHODS THEREOF

Non-Final OA §103
Filed
Jul 29, 2024
Priority
Sep 09, 2021 — provisional 63/242,048 +1 more
Examiner
VALENZUELA, PATRICIA D
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+30.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin(USPATENT: 9613931, hereinafter Lin) in view of Yu (USPATENT: 6028367, hereinafter Yu). Re claim 1 Lin discloses in Fig 1A a method of manufacturing a semiconductor package(101A/101B) module, comprising: providing a package(101A/101B) comprising a semiconductor die(102/104/106); disposing a conductive layer(108B) over the package(101A/101B); and disposing a heat dissipating module(108C) over the conductive layer(108B), the package(101A/101B), wherein the heat dissipating module(108C) is thermally coupled to and electrically isolated (by way of 118)[col4, lines 35-45] from the package(101A/101B) through the conductive layer(108B). Lin does not specifically teach the heat dissipating module(108C) propping against two opposite sides of the conductive layer(108B), Yu discloses in Fig 2, rotated 90 degrees, the heat dissipating module(34/38 of Yu) propping against sides of the conductive layer(36 of Yu) (since 36 provides support this may be interpreted as propping), It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Lin in order to have improved heat conductance and for providing additional anchoring support [col 6, lines 10-25, Yu]. In doing so, the heat dissipating module(34/38 of Yu) propping against two opposite sides of the conductive layer(36 of Yu) (since 36 provides support this may be interpreted as propping), Re claim 2 Lin and Yu disclose the method of claim 1, further comprising: forming a coating layer over the heat dissipating module(108C) by a sintering process, wherein the coating layer comprise a wicking structure. Re claim 3 Lin and Yu disclose the method of claim 1, further comprising: forming a coating layer over the heat dissipating module(108C) by a surface treatment process, wherein the coating layer comprise a low surface energy layer or a high surface energy layer. Re claim 4 Lin and Yu disclose the method of claim 1, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a microstructure in a column form extending along a stacking direction of the package(101A/101B) and the conductive layer(108B), wherein in a plane perpendicular to the stacking direction, a shape of a cross-section of the microstructure comprises a circle or ellipse-like shape, a planar or curved wall-like shape, a semi-annulus-like shape, a fin-like shape, or combinations thereof. Re claim 5 Lin and Yu disclose the method of claim 1, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a microstructure, wherein the microstructure comprises a base extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B) and a plurality of branches extending in the stacking direction and disposed over a side of the base facing away from the package(101A/101B). Re claim 6 Lin and Yu disclose the method of claim 1, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a 3D structure, wherein the 3D structure comprises at least one horizontal portion extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B), a plurality of first vertical portions extending in the stacking direction and disposed over a third side of the at least one horizontal portion facing away from the package(101A/101B), and a plurality of second vertical portions extending in the stacking direction and disposed over fourth side of the at least one horizontal portion facing to the package(101A/101B), wherein the third side is opposite to the fourth side along the stacking direction. Re claim 7 Lin discloses in Fig 1A a method of manufacturing a semiconductor package(101A/101B) module, comprising: providing a package(101A/101B) comprising a semiconductor die(102/104/106); mounting the package(101A/101B) to a circuit substrate(108A); disposing a supporting structure(126/124) on the circuit substrate(108A), the supporting structure(126/124) laterally surrounding the package(101A/101B); disposing a metallization layer(108B) over the package(101A/101B); disposing a heat dissipating module(108C) over the metallization layer(108B), the package(101A/101B), wherein the heat dissipating module(108C) is thermally coupled to and electrically isolated (by way of 118)[col4, lines 35-45] from the package(101A/101B) through the metallization layer(108B); and forming a plurality of conductive terminals(left110/right110/left120/right120) over a side of the circuit substrate(108A) opposing to the package(101A/101B) and electrically coupled to the circuit substrate(108A). Lin does not specifically teach and the heat dissipating module(108C) propping against two opposite sides of the metallization layer(108B), Yu discloses in Fig 2, rotated 90 degrees, the heat dissipating module(34/38 of Yu) propping against sides of the metallization layer(36 of Yu) (since 36 provides support this may be interpreted as propping), It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Lin in order to have improved heat conductance and for providing additional anchoring support [col 6, lines 10-25, Yu]. In doing so, the heat dissipating module(34/38 of Yu) propping against two opposite sides of the metallization layer(36 of Yu) (since 36 provides support this may be interpreted as propping), Re claim 8 Lin and Yu disclose the method of claim 7, further comprising: forming a coating layer over the heat dissipating module(108C) by a sintering process, wherein the coating layer comprise a wicking structure. Re claim 9 Lin and Yu disclose the method of claim 7, further comprising: forming a coating layer over the heat dissipating module(108C) by a surface treatment process, wherein the coating layer comprise a low surface energy layer or a high surface energy layer. Re claim 10 Lin and Yu disclose the method of claim 7, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a microstructure in a column form extending along a stacking direction of the package(101A/101B) and the conductive layer(108B), wherein in a plane perpendicular to the stacking direction, a shape of a cross-section of the microstructure comprises a circle or ellipse-like shape, a planar or curved wall-like shape, a semi-annulus-like shape, a fin-like shape, or combinations thereof. Re claim 11 Lin and Yu disclose the method of claim 7, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a microstructure, wherein the microstructure comprises a base extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B) and a plurality of branches extending in the stacking direction and disposed over a side of the base facing away from the package(101A/101B). Re claim 12 Lin and Yu disclose the method of claim 7, prior to disposing the heat dissipating module(108C) over the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a 3D structure, wherein the 3D structure comprises at least one horizontal portion extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B), a plurality of first vertical portions extending in the stacking direction and disposed over a third side of the at least one horizontal portion facing away from the package(101A/101B), and a plurality of second vertical portions extending in the stacking direction and disposed over fourth side of the at least one horizontal portion facing to the package(101A/101B), wherein the third side is opposite to the fourth side along the stacking direction. Re claim 13 Lin and Yu disclose the method of claim 7, further comprising: disposing one or more first semiconductor device on the circuit substrate(108A), the one or more first semiconductor device being electrically coupled to the package(101A/101B) through the circuit substrate(108A). Re claim 14 Lin and Yu disclose the method of claim 7, further comprising: disposing one or more second semiconductor device on the circuit substrate(108A), the one or more second semiconductor device being electrically coupled to the package(101A/101B) through the circuit substrate(108A), wherein the one or more second semiconductor device and the one or more first semiconductor device are disposed at two opposite sides of the circuit substrate(108A). Re claim 15 Lin discloses in Fig 1A a method of manufacturing a semiconductor package(101A/101B) module, comprising: providing a package(101A/101B) comprising a semiconductor die(102/104/106); disposing a conductive layer(108B) over the package(101A/101B); forming flux portions(spin-on coating)[col6, lines 40-55] over the conductive layer(108B); and mounting a heat dissipating module(108C) to the conductive layer(108B) through solder joints(120/150) therebetween by reflowing the flux portions(spin-on coating)[col6, lines 40-55], the package(101A/101B) wherein the heat dissipating module(108C) is thermally coupled to and electrically isolated (by way of 118)[col4, lines 35-45] from the package(101A/101B) through the conductive layer(108B). Lin does not specifically teach the heat dissipating module(108C) propping against two opposite sides of the conductive layer(108B), Yu discloses in Fig 2, rotated 90 degrees, the heat dissipating module(34/38 of Yu) propping against sides of the conductive layer(36 of Yu) (since 36 provides support this may be interpreted as propping), It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Lin in order to have improved heat conductance and for providing additional anchoring support [col 6, lines 10-25, Yu]. In doing so, the heat dissipating module(34/38 of Yu) propping against two opposite sides of the conductive layer(36 of Yu) (since 36 provides support this may be interpreted as propping), Re claim 16 Lin and Yu disclose the method of claim 15, wherein forming the flux portions(spin-on coating)[col6, lines 40-55] over the conductive layer(108B) comprises: placing a stencil over the conductive layer(108B), the stencil comprising a plurality of holes to partially expose the conductive layer(108B); and disposing the flux portions(spin-on coating)[col6, lines 40-55] in the plurality of holes by stencil printing. Re claim 17 Lin and Yu disclose the method of claim 16, wherein the stencil is removed from the conductive layer(108B) prior to mounting the heat dissipating module(108C) to the conductive layer(108B). Re claim 18 Lin and Yu disclose the method of claim 16, wherein the stencil is removed from the conductive layer(108B) after mounting the heat dissipating module(108C) to the conductive layer(108B). Re claim 19 Lin and Yu disclose the method of claim 15, further comprising: forming a coating layer over the heat dissipating module(108C) by a sintering process, wherein the coating layer comprise a wicking structure; and/or forming a coating layer over the heat dissipating module(108C) by a surface treatment process, wherein the coating layer comprise a low surface energy layer or a high surface energy layer. Re claim 20 Lin and Yu disclose the method of claim 15, prior to mounting the heat dissipating module(108C) to the conductive layer(108B), the method further comprising forming the heat dissipating module(108C), wherein forming the heat dissipating module(108C) comprises: forming a heat dissipating element comprising a microstructure in a column form extending along a stacking direction of the package(101A/101B) and the conductive layer(108B), wherein in a plane perpendicular to the stacking direction, a shape of a cross-section of the microstructure comprises a circle or ellipse-like shape, a planar or curved wall-like shape, a semi-annulus-like shape, a fin-like shape, or combinations thereof; forming a heat dissipating element comprising a microstructure, wherein the microstructure comprises a base extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B) and a plurality of branches, extending in the stacking direction and disposed over a side of the base facing away from the package(101A/101B); and/or forming a heat dissipating element comprising a 3D structure, wherein the 3D structure comprises at least one horizontal portion extending along a plane perpendicular to a stacking direction of the package(101A/101B) and the conductive layer(108B), a plurality of first vertical portions extending in the stacking direction and disposed over a third side of the at least one horizontal portion facing away from the package(101A/101B), and a plurality of second vertical portions extending in the stacking direction and disposed over fourth side of the at least one horizontal portion facing to the package(101A/101B), wherein the third side is opposite to the fourth side along the stacking direction. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jul 29, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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