DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the application
Claims 1-20 are pending in this application.
Claim Objections
Claim 17 is objected to because of the following informalities:
Re claim 17 recite a limitation “ the gate dielectric layer” in line 3 should read “ the first gate dielectric layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Lee et al (US20140131626A1).
Re claim 1 Lee teaches a transistor, comprising:
a channel layer (110, fig 5) [0058], wherein the channel layer (110, fig 5) comprises a graphene layer [0058] and hexagonal boron nitride (hBN) flakes [0049] dispersed in the graphene layer (110, fig 3), and orientations of the hBN flakes are substantially aligned (fig 3) [0048];
a gate stack (132/130, fig 5) [0060] over the channel layer (110, fig 5) [0060]; and source/drain regions (121/122, fig 5)[0058] aside the gate stack (132/130).
Re claim 2 Lee teaches the transistor of claim 1, wherein a content of the hBN flakes in the channel layer (110, fig 5) ranges from about 1% to about 30%. (about 1% to about 20%) [0059].
Re claim 3 Lee teaches the transistor of claim 1, wherein the channel layer has a single-crystalline structure (Graphene is a hexagonal single-layer structure formed of carbon atom, fig 5) [0005].
Re claim 6 Lee teaches the transistor of claim 1, wherein sidewalls of the source/drain regions (121, fig 5) [Lee, 0058] are in physical contact with sidewalls of the channel layer (110, fig 5) [Lee, 0058].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20140131626A1) in view of Venugopal et al (US20200075779A1).
Re claim 4. Lee teaches the transistor of claim 1,
Lee does not teach a first hBN layer and a second hBn layer disposed on two opposite sides of the channel layer and the second hBN layer is located between the gate stack and the channel layer.
Venugopal teaches a first hBN layer (112, fig 1) [0014] and a second hBN layer (128, fig 1) [0014] disposed on two opposite sides (top and bottom) of the channel layer (114, fig 1) and the second hBN layer (128, fig 1) [0014] is located between the gate stack (130/134/138, fig 1) [0021] and the channel layer (114, fig 1)[0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of to include teach a first hBN layer and a second hBn layer disposed on two opposite sides of the channel layer and the second hBN layer is located between the gate stack and the channel layer as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Venugopal in the above manner for the purpose of protecting graphite layer from degradation during fabrication [0021].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee modified by Venugopal as applied to claims 1 and 4 and further in view of Zhang et al (US20140353722A1).
Re claim 5 Lee in view of Venugopal teach the transistor of claim 4, wherein the source/drain regions (122/118 and 124/120, fig 1) [Venugopal, 0014], are in physical contact with the second hBN layer(128).
Lee and Venugopal do not teach the source/drain regions are separated from the channel layer by the second hBN layer.
Zhang teaches the source/drain regions (S and D, fig 9) [0047] are separated from the channel layer (161, fig 9) [0050] by the second hBN layer (164, fig 9)[0051].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zhang into the structure of Lee and Venugopal to include the source/drain regions are separated from the channel layer by the second hBN layer as claimed.
The ordinary artisan would have been motivated to modify Lee and Venugopal based on the teaching of Zhang in the above manner for the purpose of enhancing device performance and reliability of an heterostructure transistor [0009].
Claims 7-8, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al over Lee II et al (US20210123161A1) in view of Tang et al (US20130022813A1).
Re claim 7 Lee teaches a transistor (fig 5), comprising:
a gate electrode (132, fig 5) [0060];
a gate dielectric layer (130, fig 5) [0060];
a channel layer (110, fig 5);
wherein the channel layer (channel, fig 5) [0044] comprises a graphene layer [0044] and hexagonal boron nitride (hBN) flakes [0043] dispersed in the graphene layer (110) [0044], the graphene layer (110, fig 5) [0044] has a single-crystalline structure ((Graphene is a hexagonal single-layer structure formed of carbon atom, fig 5) [0005].
a gate stack (132/130, fig 5) [0060] over the channel layer (channel, fig 5); and source/drain regions (121/122, fig 5) [0058] aside the gate stack (130/132, fig 5).
Lee does not teach the gate dielectric disposed over the gate electrode and the channel layer disposed over the gate dielectric layer.
Lee II teaches the gate dielectric (830, fig 30B) [0210] disposed over the gate electrode (824, fig 30B) [0210] and the channel layer (842, fig 30B) [0210] disposed over the gate dielectric layer (830, fig 30B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee II into the structure of Lee to include the gate dielectric disposed over the gate electrode and the channel layer disposed over the gate dielectric layer as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Lee II in the above manner doing so a short channel effect may be prevented or minimized, and generation of leakage current and area problems may be improved [0195].
Lee and Lee II do not teach the hBN flakes have a single-crystalline structure.
Tang teaches the hBN flakes have a single-crystalline structure.(monocrystalline hBN structure, fig 1) [0020].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Tang into the structure of Lee and Lee II to include the hBN flakes have a single-crystalline structure as claimed.
The ordinary artisan would have been motivated to modify Lee and Lee II based on the teaching of Tang in the above manner for the purpose to produce a product of stable performance and high integration [0004].
Re claim 8 Lee in view of Lee II and Tang teach the transistor of claim 7, wherein a content of the hBN flakes in the channel layer (110, fig 5) [Lee, 0059] ranges from about 1% to about 30%. (about 1% to about 20%) [Lee, 0013/0015].
Re claim 13 Lee in view of Lee II teach the transistor of claim 7, wherein sidewalls of the source/drain regions (121, 122 fig 1) [Lee, 0015] are in physical contact with sidewalls of the channel layer (110, fig 1) [Lee, 0013].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee modified by Lee II and Tang as applied to claim 7 and further in view of Lee III (US20170338311A1).
Re claim 9 Lee in view of Lee II and Tang teach the transistor of claim 7,
Lee, Lee II and Tang do not teach the channel layer has an isomorphous structure.
Lee III teaches the channel layer has an isomorphous structure.(homogeneous and clean lattice structure) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Lee III to include the channel layer has an isomorphous structure as claimed.
The ordinary artisan would have been motivated to modify Lee, Lee II and Tang based on the teaching of Lee III in the above manner to achieve greater carrier mobilities[0027].
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee modified by Lee II and Tang as applied to claim 7 and further in view of Venugopal et al (US20200075779A1).
Re claim 10 Lee, Lee II and Tang do teach the transistor of claim 7,
Lee , Lee II and Tang do not teach a first hBN layer and a second hBN layer disposed on two opposite sides of the channel layer, and the first hBN layer is located between the gate dielectric layer and the channel layer.
Venugopal teaches a first hBN layer (112, fig 1) [0014] and a second hBN layer (128, fig 1) [0014] disposed on two opposite sides (top and bottom) of the channel layer (114, fig 1) and the second hBN layer (128, fig 1) [0014] is located between the gate stack (130/134/138, fig 1) [0021] and the channel layer (114, fig 1)[0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Venugopal into the structure of Le, Lee II and Tang to include teach a first hBN layer and a second hBN layer disposed on two opposite sides of the channel layer and the second hBN layer is located between the gate stack and the channel layer as claimed.
The ordinary artisan would have been motivated to modify Lee, Lee II and Tang based on the teaching of Venugopal in the above manner for the purpose of protecting graphite layer from degradation during fabrication [0021].
Re claim 12 Lee in view of Lee II and Tang teach the transistor of claim 7,
Lee, Lee II and Tang do not teach the source/drain regions are in physical contact with the gate dielectric layer and are physically separated from the gate electrode by the gate dielectric layer.
Venugopal teaches the source/drain regions (122/118 and 124/120, fig 1) [Venugopal 0014]are in physical contact with the gate dielectric layer (130, fig 1) [0017] and are physically separated from the gate electrode (134, fig 1) [0019] by the gate dielectric layer (130, fig 1) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee, Lee II and Tang into the structure of Lee, Lee II and Tang to include the source/drain regions are in physical contact with the gate dielectric layer and are physically separated from the gate electrode by the gate dielectric layer as claimed.
The ordinary artisan would have been motivated to modify Lee, Lee II and Tang based on the teaching of Venugopal in the above manner for the purpose of reducing the parasitic capacitance.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee modified by Lee II, Tang and Venugopal as applied to claim 10 and further in view of Zhang et al (US20140353722A1).
Re claim 11 Lee in view of Lee II, Tang and Venugopal teach the transistor of claim 10, wherein the source/drain regions (122/118 and 124/120, fig 1) [Venugopal, 0014], are in physical contact with the second hBN layer, (128, fig 1) [Venugopal, 0016].
Lee, Lee II, Tang and Venugopal do not teach the source/drain regions are separated from the channel layer by the second hBN layer.
Zhang teaches the source/drain regions (S and D, fig 9) [0047] are separated from the channel layer (161, fig 9) [0050] by the second hBN layer (164, fig 9)[0051].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zhang into the structure of Lee, Lee II, Tang and Venugopal to include the source/drain regions are separated from the channel layer by the second hBN layer as claimed.
The ordinary artisan would have been motivated to modify Lee, Lee II, Tang and Venugopal based on the teaching of Zhang in the above manner for the purpose of enhancing device performance and reliability of an heterostructure transistor [0009].
Claims 14-16 , 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ohmaru et al (US20200304691A1).
Re claim 14 Lee teaches a transistor (fig 5), comprising: a first gate electrode (132, fig 1) [0060];
a first gate dielectric layer (130, fig 1) [0060];
a channel layer (110, fig 1) [0060];
wherein the channel layer (110, fig 1) comprises hexagonal boron nitride (hBN) flakes [ figs 3 and 4) [0048] and a graphene layer (Graphene channel, fig 1) [0058] laterally dispersed around the hBN flakes (see fig 3 and, and orientations of the hBN flakes [0058] are substantially aligned (fig 3);
a gate stack over the channel layer (130/132, fig 5) [0060],
source/drain regions (121/122, fig 5) aside the gate stack (130/132, fig 5).
Lee does not teach the first gate dielectric layer disposed on the first gate electrode, the channel layer disposed over the first gate dielectric layer and the gate stack comprises a second gate dielectric layer and a second gate electrode on the second gate dielectric layer.
Ohmaru teaches the first gate dielectric layer (403, fig 21B) [0262] disposed on the first gate electrode (451,fig 21B) [0332], the channel layer (421, fig 21B) [0265] disposed over the first gate dielectric layer (403, fig 21B) and the gate stack (443/411, fig 21B) [0336] comprises a second gate dielectric layer (411, fig 21B) [0346] and a second gate electrode (443, fig 21B) on the second gate dielectric layer (411, fig 21B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Ohmaru to include the first gate dielectric layer disposed on the first gate electrode, the channel layer disposed over the first gate dielectric layer and the gate stack comprises a second gate dielectric layer and a second gate electrode on the second gate dielectric layer as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Ohmaru in the above manner for the purpose of improvement in field effect mobility of the transistor [0273].
Re claim 15 Lee in view of Ohmaru teach the transistor of claim 14, wherein a content of the hBN flakes in the channel layer (110, fig 5)[Lee 0059] ranges from about 1% to about 30%. (about 1% to 20%) [Lee, 0013/0015].
Re claim 16 Lee in view of Ohmaru teach the transistor of claim 14, wherein the channel layer has a single-crystalline structure (Graphene is a hexagonal single-layer structure formed of carbon atom, fig 5) [Lee, 0005].
Re claim 19 Lee in view of Ohmaru teach the transistor of claim 14, wherein the first gate electrode (451, fig 21B) [Ohmaru, 0332] and the first gate dielectric layer (403, fig 21B) [Ohmaru, 0339] are larger than the channel layer (421, fig 21B) [Ohmaru 265].
Re claim 20 Lee in view of Ohmaru teach the transistor of claim 19, wherein sidewalls of the source/drain regions (121, fig 5) [Lee, 0058] are in physical contact with sidewalls of the channel layer (110, fig 5) [Lee, 0058].
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee modified by Ohmaru as applied to claim 14 and further in view of Venugopal et al (US20200075779A1) and Zhang et al (US20140353722A1).
Re claim 17 Lee in view of Ohmaru teach the transistor of claim 14,
Lee and Ohmaru do not teach a first hBN layer and a second hBN layer disposed on two opposite sides of the channel layer, the first hBN layer is located between the gate dielectric layer and the channel layer,
Venugopal teach a first hBN layer (128, fig 1) [0016] and a second hBN layer (112, fig 1) [0014] disposed on two opposite sides of the channel layer (114, fig 1) [0014], the first hBN layer (128, fig 1) [0016] is located between the gate dielectric layer (130, fig 1) [0017] and the channel layer (114, fig 1) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Venugopal into the structure of Lee and Ohmaru to include a first hBN layer and a second hBN layer disposed on two opposite sides of the channel layer, the first hBN layer is located between the gate dielectric layer and the channel layer as claimed.
The ordinary artisan would have been motivated to modify Lee and Ohmaru based on the teaching of Venugopal in the above manner for the purpose of protecting graphite layer from degradation during fabrication [0021].
Lee, Ohmaru and Venugopal do not teach the second gate dielectric layer is in physical contact with the second hBN layer.
Zhang does teach the second gate dielectric layer (162, fig 7D) [0047] is in physical contact with the second hBN layer (196, fig 7D) [0058].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Lee, Ohmaru and Venugopal to include the second gate dielectric layer is in physical contact with the second hBN layer as claimed.
The ordinary artisan would have been motivated to modify Lee, Ohmaru and Venugopal based on the teaching of Zhang in the above manner for the purpose of improving reliability during high-power operation [0011].
Re claim 18 Lee in view of Ohmaru and Venugopal teach the transistor of claim 17, wherein the source/drain regions (108/110, fig 5) [Zhang, 0058] are in physical contact with the second hBN layer (196, fig 5) [Zhang, 0058] .
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al (US 20200109487A1) teaches a method for 2D epitaxial growth comprising: forming a single crystalline h-BN template and Dresselhaus et al (US20170170260A1) teaches a device with a two-dimensional heterostructure comprising graphene with hBN.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/24/26
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