DETAILED ACTION
Allowable Subject Matter
Claims 1-16 are allowed (once the double patenting rejection below is overcome).
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 20 recites in part “wherein a material of the shielding layer comprises a semiconductor material”.
The reason why this is indicated as allowable subject matter is explained directly below.
The following is an examiner’s statement of reasons for allowance.
Claim 1 recites in part “a light shielding element, located on the first dielectric layer and comprising: a semiconductor layer, electrically isolated from the memory element, wherein the light shielding element is overlapped with at least a part of the memory element on a plane along a stacking direction of the memory element and the light shielding element, wherein the stacking direction is normal to the plane”.
Claim 11 recites in part “a shielding layer, located over and electrically isolated from the gate electrode, wherein a material of the shielding layer comprises a semiconductor material; and a driving circuit adjacent to the storage device”.
This case is a child of S/N 17/874,321. The claim limitations recited above (in claims 1, 11 & 20) are virtually identical to the limitations indicated as allowable subject matter in the parent case, and therefore, in the instant case are indicated as allowable (in case of claims 1 & 11) or as an allowable subject matter (in case of claim 20) for virtually the same reasons as in the parent case (see NOA, dated 10/07/2024, in case S/N 17/874,321 for details).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 & 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 & 10 of U.S. Patent No. 12,218,159. Although the claims at issue are not identical, they are not patentably distinct from each other:
1. An image sensor, comprising: a storage device, comprising: a memory element; a first dielectric layer, located over the memory element; and a light shielding element, located on the first dielectric layer and comprising: a semiconductor layer, electrically isolated from the memory element,
1. An image sensor, comprising: a storage device, comprising: a memory element, comprising: a storage node; and a storage transistor gate, disposed over the storage node; and a light shielding element, disposed over the memory element and comprising: a semiconductor layer, electrically isolated from the memory element (reads on “first dielectric layer” also, as an example of what can be used for “electrical isolation”; at least, using a dielectric layer is a notoriously well-known way of electrically isolating various objects in semiconductor industry),
wherein the light shielding element is overlapped with at least a part of the memory element on a plane along a stacking direction of the memory element and the light shielding element, wherein the stacking direction is normal to the plane.
wherein a projection of the light shielding element covers a projection of the storage transistor gate on a plane along a stacking direction of the memory element and the light shielding element.
10. An image sensor, comprising: a photosensitive device; a storage device, adjacent to the photosensitive device, comprising: a substrate; a P-N junction, embedded in the substrate; a gate electrode, covering the P-N junction; and
11. An image sensor, comprising: a photosensitive device; a storage device adjacent to the photosensitive device, comprising: a substrate; a P-N junction, located within the substrate; a gate electrode, located over the P-N junction; and
a shielding structure, disposed over the substrate and electrically isolated from the gate electrode, wherein the shielding structure comprise: …, wherein a projection of the first portion is overlapped with a projection of the gate electrode on a plane along a stacking direction of the substrate and the gate electrode, wherein the first shielding layer is made of a semiconductor layer; …; a driving circuit, adjacent to the storage device; ...
a shielding layer, located over and electrically isolated from the gate electrode, wherein a material of the shielding layer comprises a semiconductor material; and a driving circuit adjacent to the storage device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2014/0015013) by Arakawa et al (“Arakawa”).
Regarding claim 17, Arakawa discloses in FIG. 22 and related text, e.g., an image sensor, comprising:
a photosensitive device (131);
a storage device (164; see par. 22; things under light shield are part of “memory unit”) adjacent to the photosensitive device, comprising: a substrate (151);
a P-N junction, located within the substrate (151 is p-type; 164 is n-type; interface between them is a P-N junction;
a gate dielectric layer (par. 73; “gate insulating film (not illustrated in the drawings)), located on the substrate (see par. 73) and over the P-N junction (by definition);
a gate electrode (342), located over the gate dielectric layer (par. 73, and by definition);
a first dielectric layer (184), having a first portion located on the gate electrode (portion of 184 directly over 342; say, the left one) and a second portion located on the substrate (portion of 184 directly over substrate; say, to the left of 342), the first portion connecting to the second portion (see FIG. 22);
a shielding layer (185), located over and electrically isolated from the gate electrode; and
a second dielectric layer (186), over the shielding layer and the gate electrode (see FIG. 22), wherein the shielding layer is at least overlapped with edges of the gate electrode along a stacking direction of the substrate and the gate electrode (see FIG. 22);
a driving circuit adjacent to the storage device (see FIG. 1; driving circuit is adjacent); and
an interconnect, disposed over and electrically coupled to the photosensitive device, the storage device, and the driving circuit (87 in FIG. 2, for example; all the wiring that is involved is shown in FIG. 1).
Regarding claim 18, Arakawa discloses in FIG. 22 and related text, e.g., wherein the shielding layer comprises:
a first plate structure having a first shielding portion (portion of 185 directly above 342) with a recess (351-2) formed therein and a second shielding portion connected to and surrounding the first shielding portion (best seen in FIG. 22, B portion; area of 185 outside of 342), wherein the first shielding portion extends on the first portion of the first dielectric layer (as was previously defined), the recess is located atop the gate electrode (351-2 is exactly there), and the second shielding portion extends on the second portion of the first dielectric layer (as was previously defined in claim 17; best seen in combination of FIG. 22, A and B portions).
Regarding claim 19, Arakawa discloses in FIG. 22 and related text, e.g., wherein the shielding layer comprises:
a second plate structure (consider “second plate structure” to be everything that is not “first plate structure” (not directly above 342) having a third shielding portion (everything that is not “first … portion” or “second … portion”; includes 185 around 351-1) with a recess (351-1; this may merit a 112, 2nd rejection; “a recess”? how is it related to “a recess” specified in claim 18? Examiner will keep writing rejection of this claim, but at this point Examiner has no clue what is actually being claimed; please in response specify the specific drawing and the specific one or two (?) recess(es)) formed therein, wherein the third shielding portion extends on (“above”) the first portion of the first dielectric layer (at least some portions of 185 directly near 351-1 are above “first dielectric layer”; thus meeting limitations), and the recess is located atop of the gate electrode (this may merit an another 112, 2nd; and now we have “the recess”; which one?; presumed to be 351-2 for purposes of rejection).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/05/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights