DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 29, 2024 and January 14, 2026 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING AN INTERCONNECT STRUCTURE INCLUDING A TRANSITION METAL CHALCOGENIDE BARRIER LAYER.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2020/0312775 A1).
Claim 1, Lee discloses a device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) comprising:
a substrate (semiconductor substrate 300, [0031], Fig. 3D);
a dielectric layer (dielectric layers 301 and 305 include a dielectric layer, hereinafter, dielectric layer 301/305, [0031], Fig. 3D) over the substrate 300 (dielectric layer 301/305 are over the substrate 300, [0031], Fig. 3D); and
a conductive interconnect (interconnect vias are formed within the via openings 306a and 306b, hereinafter, conductive interconnect 306a/306b, 0035], Figs. 3C and 3D) in the dielectric layer 301/305 (conductive interconnect 306a/306b are in the dielectric layer 301/305, 0035], Figs. 3C and 3D), the conductive interconnect 306a/306b comprising:
a barrier/adhesion layer (layers of two dimensional material 308 are a barrier/adhesion layer, hereinafter, barrier/adhesion layer 308, [0033], Fig. 3D), the barrier/adhesion layer 308 comprising a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2 (barrier/adhesion layer 308 comprises a material, the material having a chemical formula MXn, with M being a transition metal element (i.e. M is a transition metal selected from the group consisting of Sc, Y, La, Ac, Ti, Zr, Hf, Rf, V, Nb, Ta, Fa, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pb, Pt, Cu, Ag, Au, Zn, Cd, Hg), X being a first chalcogen element (i.e. X is a chalcogen selected from the group consisting of S, Se and Te), and n being between o.5 and 2 (i.e. n is 2), [0016] and [0033], Fig. 3D); and
a conductive layer (interconnect metal layer 309 is a conductive layer, hereinafter, conductive layer 309, [0037], Fig. 3D) over the barrier/adhesion layer 308 (conductive layer 309 is over the barrier/adhesion layer 308, [0037], Fig. 3D).
Claim 6, Lee discloses the device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) of claim 1.
Lee discloses wherein the barrier/adhesion layer 308 has a layered structure (barrier/adhesion layer 308 has a layered structure, [0018], Fig. 3D).
Claim 7, Lee discloses the device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) of claim 1.
Lee discloses wherein the barrier/adhesion layer 308 has a thickness between about 0.5 nm and about 3 nm (barrier/adhesion layer 308 has a thickness between about 0.5 nm and about 1 nm (i.e. less than 1 nm), [0018], Fig. 3D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 8-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Naylor (US 2021/0098387 A1).
Claim 2, Lee discloses the device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) of claim 1.
Lee does not explicitly disclose wherein the conductive layer comprises a seed layer over and in physical contact with the barrier/adhesion layer.
However, Naylor discloses wherein the conductive layer (Naylor, fill metal 322 is a conductive layer, hereinafter, conductive layer 322, [0035], Figs. 3A and 4A; Lee, conductive layer 309, [0037], Fig. 3D) comprises a seed layer over and in physical contact with the barrier/adhesion layer (Naylor, conductive layer 322 comprises a seed layer 321 over and in physical contact with the barrier/adhesion layer 315/722, [0035], Figs. 3A and 4A; Lee, conductive layer 309 and barrier/adhesion layer 308, [0037], Fig. 3D). The combination to utilize a seed layer in combination with an above lying conductive metal fill layer ensures formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers results in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a seed layer in combination with an above lying conductive metal fill layer to ensure formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers to result in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Claim 3, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 2.
Lee/Naylor discloses wherein a top surface of the dielectric layer is level with a top surface of the seed layer (Naylor, top surface of the dielectric layer 210 is level with a top surface of the seed layer 321, [0054], Figs. 3A and 4A; Lee, conductive layer 309 and barrier/adhesion layer 308, [0037], Fig. 3D).
Claim 4, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 2.
Lee/Naylor discloses wherein the conductive layer further comprises a conductive fill layer over the seed layer (Naylor, conductive layer 322 further comprises a conductive fill layer 322 (i.e. hybrid bonding features 401 are stacked) over the seed layer 321, [0057], Fig. 6B; Lee, conductive layer 309 and barrier/adhesion layer 308, [0037], Fig. 3D).
Claim 5, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 4.
Lee/Naylor discloses wherein a top surface of the dielectric layer is level with a top surface of the conductive fill layer (Naylor, top surface of the dielectric layer 210 is level with a top surface of the conductive fill layer 322, [0054], Figs. 3A and 4A; Lee, conductive layer 309 and barrier/adhesion layer 308, [0037], Fig. 3D).
Claim 8, Lee discloses a device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) comprising:
a substrate (semiconductor substrate 300, [0031], Fig. 3D);
a first dielectric layer (dielectric layer 305 is a first dielectric layer, hereinafter, first dielectric layer 305, [0031], Fig. 3D) over the substrate 300 (first dielectric layer 305 is over the substrate 300, [0031], Fig. 3D);
a conductive via (interconnect vias are formed within the via openings 306a and 306b, hereinafter, conductive via 306a/306b, 0035], Figs. 3C and 3D) in the first dielectric layer 305 (conductive via 306a/306b are in the first dielectric layer 305, 0035], Figs. 3C and 3D), the conductive via 306a/306b comprising:
a first barrier/adhesion layer (another layer of two dimensional material 308b is a first barrier/adhesion layer, hereinafter, first barrier/adhesion layer 308b, [0033], Fig. 3D) comprising a first material, the first material having a first chemical formula MXn, with M being a first transition metal element, X being a first chalcogen element, and n being between o.5 and 2 (first barrier/adhesion layer 308b comprises a first material, the first material having a first chemical formula MXn, with M being a first transition metal element (i.e. M is a transition metal selected from the group consisting of Sc, Y, La, Ac, Ti, Zr, Hf, Rf, V, Nb, Ta, Fa, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pb, Pt, Cu, Ag, Au, Zn, Cd, Hg), X being a first chalcogen element (i.e. X is a chalcogen selected from the group consisting of S, Se and Te), and n being between o.5 and 2 (i.e. n is 2), [0016] and [0033], Fig. 3D); and
a first conductive layer (interconnect metal layer 309 over the first via opening 306a is a first conductive layer, hereinafter, first conductive layer 309a, [0037], Fig. 3D) over the first barrier/adhesion layer 308a (first conductive layer 309a is over the first barrier/adhesion layer 308a, [0037], Fig. 3D);
a second dielectric layer (dielectric layer 301 is a second dielectric layer, hereinafter, second dielectric layer 301, [0031], Fig. 3D) over the first dielectric layer 305 and the conductive via 306a/306b (second dielectric layer 301 is over the first dielectric layer 305 and the conductive via 306a/306b (i.e. when the resultant device is inverted), [0031], Fig. 3D); and
a conductive line (conductive lines 302a and 302b include a conductive line, hereinafter, conductive line 302a/302b, [0036], Fig. 3D) in the second dielectric layer 301 (conductive line 302a/302b is in the second dielectric layer 301, [0036], Fig. 3D), the conductive line 302a/302b comprising:
a second barrier/adhesion layer (layer of two dimensional material 308a is a second barrier/adhesion layer, hereinafter, second barrier/adhesion layer 308a, [0033], Fig. 3D) comprising the first material (second barrier/adhesion layer 308a may comprise the first material (i.e. M is a transition metal selected from the group consisting of Sc, Y, La, Ac, Ti, Zr, Hf, Rf, V, Nb, Ta, Fa, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pb, Pt, Cu, Ag, Au, Zn, Cd, Hg), X being a second chalcogen element (i.e. X is a chalcogen selected from the group consisting of S, Se and Te), and n being between o.5 and 2 (i.e. n is 2), [0016] and [0033], Fig. 3D).
Lee does not explicitly disclose a second conductive layer over the second barrier/adhesion layer.
However, Naylor/Lee disclose a second conductive layer (Naylor, second conductive layer 322 within upper hybrid bonding feature 401, [0057], Fig. 6B; Lee, interconnect metal layer 309 over the second via opening 306b is a second conductive layer, hereinafter, second conductive layer 309b, [0037], Figs. 3C and 3D) over the second barrier/adhesion layer (Naylor, second conductive layer 322 is over the second barrier/adhesion layer 722, [0057], Fig. 6B; Lee, second conductive layer 309b is over the second barrier/adhesion layer 308a, [0037], Figs. 3C and 3D). The combination to utilize an additional conductive fill layer in combination with an adjacent adhesion/barrier layer ensures formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers results in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional conductive fill layer in combination with an adjacent adhesion/barrier layer to ensure formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers results in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Claim 9, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the first barrier/adhesion layer has a layered structure (Lee, first barrier/adhesion layer 308b has a layered structure (i.e. barrier/adhesion layer 308 may be formed of first and second barrier/adhesion layers 308a and 308b, wherein each barrier/adhesion layer 308a/308b may comprise between 2 to 6 sub-layers), [0015], Fig. 3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B).
Claim 10, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the first conductive layer comprises a first seed layer over the first barrier/adhesion layer (Naylor, first conductive layer 322 comprises a first seed layer 321 over the first barrier/adhesion layer 315/722, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a over first barrier/adhesion layer 308b, [0037], Fig. 3D), the first seed layer being an uppermost layer of the conductive via (Naylor, first seed layer 321 is in an uppermost layer of the conductive via 401, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a over first barrier/adhesion layer 308b, [0037], Fig. 3D).
Claim 11, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the first conductive layer (Naylor, first conductive layer 322, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D) comprises:
a first seed layer over the first barrier/adhesion layer (Naylor, first conductive layer 322 comprises a first seed layer 321 over the first barrier/adhesion layer 315/722, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a over first barrier/adhesion layer 308b, [0037], Fig. 3D); and
a first conductive fill layer over the first seed layer (Naylor, first conductive layer 322 is a first conductive fill layer and is over the first seed layer 321, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D), a top surface of the first conductive fill layer being level with a top surface of the first dielectric layer (Naylor, a top surface of the first conductive layer 322 is level with a top surface of the first dielectric layer 210, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a and first dielectric layer 305, [0037], Fig. 3D).
Claim 12, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the second conductive layer comprises a second seed layer over the second barrier/adhesion layer (Naylor, conductive layer 322 is a second conductive fill layer on top of the first conductive fill layer and comprises a second seed layer 321 over the second barrier/adhesion layer 722, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D), the second seed layer being an uppermost layer of the conductive line (Naylor, second seed layer 321 being an uppermost layer of the conductive line 402, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D).
Claim 13, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the second conductive layer (Naylor, second conductive layer 322, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D) comprises:
a second seed layer over the second barrier/adhesion layer (Naylor, second seed layer 321 over the second barrier/adhesion layer 722, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D); and
a second conductive fill layer over the second seed layer (Naylor, second conductive fill layer 322 over the second seed layer 321, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D), a top surface of the second conductive fill layer being level with a top surface of the second dielectric layer (Naylor, a top surface of the second conductive fill layer 322 being level with a top surface of the second dielectric layer 210, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D).
Claim 14, Lee/Naylor discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 8.
Lee/Naylor discloses wherein the second barrier/adhesion layer is in physical contact with the first conductive layer (Naylor, second barrier/adhesion layer 722 is in physical contact with the first conductive layer 322, [0035], Fig. 7B; Lee, first conductive layer 309a, [0037], Fig. 3D).
Claim 15, Lee discloses a device (semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D) comprising:
a substrate (semiconductor substrate 300, [0031], Fig. 3D);
a plurality of dielectric layers (dielectric layers 301 and 305 are a plurality of dielectric layers, hereinafter, plurality of dielectric layers 301/305, [0031], Fig. 3D) over the substrate 300 (plurality of dielectric layers 301/305 are over the substrate 300, [0031], Fig. 3D);
a conductive via (interconnect vias are formed within the via openings 306a and 306b, hereinafter, conductive via 306a/306b, 0035], Figs. 3C and 3D) in one or more of the plurality of dielectric layers 301/305 (conductive via 306a/306b are in one or more of the plurality of dielectric layers 301/305, 0035], Figs. 3C and 3D), the conductive via 306a/306b comprising:
a first barrier/adhesion layer (another layer of two dimensional material 308b is a first barrier/adhesion layer, hereinafter, first barrier/adhesion layer 308b, [0033], Fig. 3D) comprising a first material, the first material having a first chemical formula MXn, with M being a first transition metal element, X being a first chalcogen element, and n being between o.5 and 2 (first barrier/adhesion layer 308b comprises a first material, the first material having a first chemical formula MXn, with M being a first transition metal element (i.e. M is a transition metal selected from the group consisting of Sc, Y, La, Ac, Ti, Zr, Hf, Rf, V, Nb, Ta, Fa, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pb, Pt, Cu, Ag, Au, Zn, Cd, Hg), X being a first chalcogen element (i.e. X is a chalcogen selected from the group consisting of S, Se and Te), and n being between o.5 and 2 (i.e. n is 2), [0016] and [0033], Fig. 3D); and
a first conductive layer (interconnect metal layer 309 over the first via opening 306a is a first conductive layer, hereinafter, first conductive layer 309a, [0037], Fig. 3D) over the first barrier/adhesion layer 308a (first conductive layer 309a is over the first barrier/adhesion layer 308a, [0037], Fig. 3D); and
a conductive line (conductive lines 302a and 302b include a conductive line, hereinafter, conductive line 302a/302b, [0036], Fig. 3D) in one or more of the plurality of dielectric layers 301/305 (conductive line 302a/302b is in one or more of the plurality of dielectric layers 301/305, [0036], Fig. 3D), the conductive line 302a/302b being in electrical contact with the conductive via 306a/306b (conductive line 302a/302b being in electrical contact with the conductive via 306a/306b, [0036], Fig. 3D), the conductive line 302a/302b comprising:
a second barrier/adhesion layer (layer of two dimensional material 308a is a second barrier/adhesion layer, hereinafter, second barrier/adhesion layer 308a, [0033], Fig. 3D) comprising a second material, the second material having a second chemical formula MXn, with M being a second transition metal element, X being a second chalcogen element, and n being between 0.5 and 2 (second barrier/adhesion layer 308a comprises a second material, the second material having a second chemical formula MXn, with M being a second transition metal element (i.e. M is a transition metal selected from the group consisting of Sc, Y, La, Ac, Ti, Zr, Hf, Rf, V, Nb, Ta, Fa, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pb, Pt, Cu, Ag, Au, Zn, Cd, Hg), X being a second chalcogen element (i.e. X is a chalcogen selected from the group consisting of S, Se and Te), and n being between o.5 and 2 (i.e. n is 2), [0016] and [0033], Fig. 3D).
Lee does not explicitly disclose a second conductive layer over the second barrier/adhesion layer.
However, Naylor/Lee disclose a second conductive layer (Naylor, second conductive layer 322 within upper hybrid bonding feature 401, [0057], Fig. 6B; Lee, interconnect metal layer 309 over the second via opening 306b is a second conductive layer, hereinafter, second conductive layer 309b, [0037], Figs. 3C and 3D) over the second barrier/adhesion layer (Naylor, second conductive layer 322 is over the second barrier/adhesion layer 722, [0057], Fig. 6B; Lee, second conductive layer 309b is over the second barrier/adhesion layer 308a, [0037], Figs. 3C and 3D). The combination to utilize an additional conductive fill layer in combination with an adjacent adhesion/barrier layer ensures formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers results in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional conductive fill layer in combination with an adjacent adhesion/barrier layer to ensure formation of a resultant two dimensional transition metal chalcogenide material, wherein the resultant diffusion of the conductive layer into the adjacent layers results in reduced outdiffusion of fill metal through hybrid bonded surfaces and may therefore be commercially advantageous (Naylor, [0003]).
Claim 17, Lee discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 15.
Lee/Naylor discloses wherein the first conductive layer (Naylor, first conductive layer 322, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D) comprises a first seed layer (Naylor, first conductive layer 322 comprises a first seed layer 321, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D), wherein the conductive via further comprises a first conductive fill over the first seed layer (Naylor, first conductive layer 322 is a first conductive fill layer and is over the first seed layer 321, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D).
Claim 18, Lee discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 15.
Lee/Naylor discloses wherein the second conductive layer comprises a second seed layer (Naylor, conductive layer 322 is a second conductive fill layer on top of the first conductive fill layer and comprises a second seed layer 321 over the second barrier/adhesion layer 722, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D), wherein the conductive line further comprises a second conductive fill over the second seed layer (Naylor, second conductive fill layer 322 over the second seed layer 321, [0035], Figs. 3A and 4A; Lee, first conductive layer 309a, [0037], Fig. 3D).
Claim 19, Lee discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 15.
Lee/Naylor discloses wherein the first barrier/adhesion layer comprises a plurality of sub-layers (Lee, first barrier/adhesion layer 308b comprises a plurality of sub-layers (i.e. barrier/adhesion layer 308 may be formed of first and second barrier/adhesion layers 308a and 308b, wherein each barrier/adhesion layer 308a/308b may comprise between 2 to 6 sub-layers), [0015], Fig. 3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B).
Claim 20, Lee discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 15.
Lee/Naylor discloses wherein the first chalcogen element comprises sulfur (Lee, first barrier/adhesion layer 308b comprises a first material, the first material having a first chemical formula MXn, with X being a first chalcogen element selected from the group consisting of S, Se and Te (i.e. first chalcogen may comprise sulfur), [0016] and [0033], Fig. 3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Naylor, and further in view of Kung (US 2020/0043777 A1).
Claim 16, Lee discloses the device (Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B) of claim 15.
Lee/Naylor does not explicitly disclose wherein the second barrier layer completely separates the first conductive layer from the second conductive layer.
However, Kung discloses wherein the second barrier layer completely separates the first conductive layer from the second conductive layer (Kung, second barrier layer 131 completely separates the first conductive layer 132 from the second conductive layer 124, [0058], Fig. 5E’; Lee, semiconductor device structure 330 is a device, hereinafter, device 330, [0031], Figs. 3A-3D; Naylor, bonding workpiece 500 is a device, hereinafter, device 500, [0046], Figs. 4A and 7B). The combination to utilize an additional barrier layer to separate conductive layers from each other would improve the adhesion between the above and under lying layers (Kung, [0070]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional barrier layer to separate conductive layers from each other to improve the adhesion between the above and under lying layers (Kung, [0070]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2021/0388488 A1) discloses a device (Fig. 6C) comprising:
a substrate 100; a dielectric layer 500 over the substrate 100; and a conductive interconnect 200/300/400A/400B/600 in the dielectric layer 500, the conductive interconnect 200/300/400A/400B/600 comprising:
a barrier/adhesion layer 300, the barrier/adhesion layer 300 comprising a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2 (i.e. two-dimensional transition metal chalcogenide (TMC), Abstract); and a conductive layer 400A/400B over the barrier/adhesion layer 300.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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