DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8 & 16-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xu et al. US (2022/0115375) [Hereinafter Xu].
Regarding claim 8, Xu teaches A method, comprising: forming, in a device region of a semiconductor wafer,
a plurality of fin structures in a substrate of the semiconductor wafer[annotated fig. 9],
wherein the plurality of fin structures comprises:
a first fin structure [annotated fig. 9], and
a second fin structure [annotated fig. 9] that is located adjacent to the first fin structure and located closer to a center of the semiconductor wafer relative to the first fin structure[annotated fig. 9]; and forming
a merged source/drain region [fig. 9, source/drain region 120A, para 30] on the first fin structure [annotated fig. 9] and the second fin structure [annotated fig. 9] ,
wherein the merged source/drain region [fig. 9, source/drain region 120A] is tilted toward the center of the semiconductor wafer [annotated fig. 9] .
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XU, ANNOTATED FIG. 9
Regarding claim 16, Xu teaches The method of claim 8, further comprising:
forming an opening in a dielectric layer [fig. 9, insulating portion 170, para 42] to the merged source/drain region (fig. 9, 120A); and
forming a conductive structure [fig. 9, contact structure 190, para 42] on the merged source/drain region (fig. 9, 120A) in the opening.
Regarding claim 17, Xu teaches The method of claim 16,
wherein the conductive structure (fig. 9, 190) laterally extends over the plurality of fin structures [annotated fig. 9].
Regarding claim 18, Xu teaches A method, comprising: forming, in a device region of a semiconductor wafer,
a plurality of fin structures [annotated fig. 9] in a substrate [fig. 9, substrate 101, para 51] of the semiconductor wafer,
wherein the plurality of fin structures comprises:
a first fin structure [annotated fig. 9],
a second fin structure [annotated fig. 9], and
a third fin structure [annotated fig. 9];
forming a merged source/drain region [fig. 9, source/drain 120A, para 58] on the first fin structure and the second fin structure [annotated fig. 9]; and
forming a non-merged source/drain region [annotated fig. 9, 120B, para 80 wherein the region comprises a silicon (Si) epitaxial layer –not a merge structure like 120A] on the third fin structure [annotated fig. 9],
wherein a height of a top surface of the merged source/drain region (fig. 9, 120A) is different than a height of a top surface of the non-merged source/drain region (fig. 9, 120B).
Regarding claim 19, Xu teaches The method of claim 18,
wherein a width of the merged source/drain region (fig. 9, 120A) is greater than a width of the non-merged source/drain region (fig. 9, 120B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Xu, Cho et al. (US 2021/0098577) [Hereinafter Cho], & More et al. (US 2019/0148551) [Hereinafter More].
Regarding claim 1 Xu teaches A method, comprising:
forming, in a device region of a semiconductor wafer,
a plurality of fin structures [annotated fig. 9] in a substrate [fig. 9, substrate 101, para 64] of the semiconductor wafer,
wherein the plurality of fin structures comprises:
a first fin structure [annotated fig. 9], and
a second fin structure that is located adjacent to the first fin structure and located closer to a center of the semiconductor wafer relative to the first fin structure [annotated fig. 9];
a merged source/drain region [fig. 9, source/drain region 120A, para 30] on the first fin structure [annotated fig. 9] and the second fin structure [annotated fig. 9],
wherein the merged source/drain region is tilted toward the center of the semiconductor wafer [annotated fig. 9].
Xu fails to explicitly disclose a spacer layer on tops and sidewalls of the plurality of fin structures;
etching the plurality of fin structures,
wherein etching the plurality of fin structures results in formation of a first fin sidewall spacer and a second fin sidewall spacer on opposing sides of the first fin structure.
However Cho teaches a spacer layer on tops and sidewalls [fig. 2B, dielectric layer 162] of the plurality of fin structures [fig. 2B 105A];
etching the plurality of fin structures,
wherein etching the plurality of fin structures results in formation of a first fin sidewall spacer [fig. 5, spacer 120, para 32] and a second fin sidewall spacer [fig. 5, blocking layer 125, para 32] on opposing sides of the first fin structure.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the plurality of fins to have sidewall spacers to provide electrical isolation and self-alignment masking for the source/drain regions.
Xu/Cho fails to explicitly teach the height of the first sidewall spacer being greater relative to a height of the second fin sidewall spacer.
While Xu/Cho notes the merged source/drain region tilted toward the center and the use sidewall spacer height to suppress the growth of the source/drain regions.
More teaches the height of the first sidewall spacer [fig. 9, inner spacer 600/610] being greater relative to a height of the second fin sidewall spacer [fig. 9, outer spacer 600/610]. Furthermore para 45 teaches the spacer stack modulates the final size/volume of the source/drain regions].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the size/height of the merged source/drain region to modulated by the sidewall spacers which directly optimizes transistor drive current and reduces parasitic capacitance.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xu, Cho, & More as applied to claim 1 and further in view of Mao et al. (CN105097532A).
Regarding claim 6, Xu/Cho/More teaches Mao teaches The method of claim 1.
Xu/Cho/More fails to explicitly disclose wherein etching the plurality of fin structures comprises: providing a plasma in a processing chamber of an etch tool; and alternating, while providing the plasma to the semiconductor wafer in the processing chamber, between: a first combination including a first power setting for the plasma and a first non-zero bias voltage for a chuck in the processing chamber, and a second combination including a second power setting for the plasma and a second non-zero bias voltage for the chuck.
However Mao teaches wherein etching the plurality of fin structures comprises:
providing a plasma in a processing chamber of an etch tool; and
alternating, while providing the plasma to the semiconductor wafer in the processing chamber, between:
a first combination including a first power setting for the plasma and a first non-zero bias voltage for a chuck in the processing chamber [ “the etching gas used in the first angle plasma etching includes . . .the etch voltage is 5 mTorr to 50 mTorr, the power is 400 W to 750 W, and the bias voltage is 80 V to 250 V. The bias voltage forms a first tilt angle between the electric field direction and the normal to the surface of the semiconductor substrate.” , and
a second combination including a second power setting for the plasma and a second non-zero bias voltage for the chuck [“Optionally, the etching gas used in the second angle plasma etching . . . the power is 400 W to 750 W, and the bias voltage is 80 V to 250 V. The bias voltage forms a second tilt angle between the direction of the electric field and the normal of the surface of the semiconductor substrate.”].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize plasma with independent bias voltage control to etch semiconductor fins to achieve high anisotropy thereby creating near perfect fin profiles to prevent electrical leakage.
Claims 9-11 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu as applied to claim 8 & 16-19 and further in view of Cho.
Regarding claim 9, Xu teaches The method of claim 8.
Xu fails to explicitly disclose forming
a first fin sidewall spacer on a first side of the first fin structure and
a second fin sidewall spacer on a second side of the first fin structure.
However Cho teaches forming
a first fin sidewall spacer [fig. 4, spacer 120, para 21] on a first side of the first fin structure [annotated fig. 4] and
a second fin sidewall spacer [fig. 4, blocking layer 125, para 29] on a second side of the first fin structure [annotated fig. 4].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the fins to comprise sidewall spacers to provide isolation and prevent shorts and self-aligned masking for source/drain offset.
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Cho, ANNOTATED FIG. 4
Regarding claim 10 Xu/Cho teaches The method of claim 9,
wherein a height of the first fin sidewall spacer (Cho, fig. 4, 120) is greater than a height of the second fin sidewall spacer (Cho, fig. 4, 125).
Regarding claim 11, Xu/Cho teaches The method of claim 9,
wherein forming the first fin sidewall spacer (Cho, fig. 4, 120) and the second fin sidewall spacer (Cho, fig. 4, 125) comprises:
forming a spacer layer around the plurality of fin structures; and etching the spacer layer [Cho, para 7 discloses etching of insulating layer to form a blocking layer and para 71 discloses the space forming layer SR is etched to form the spacers 120].
Regarding claim 20, Xu teaches, The method of claim 18,
wherein the merged source/drain region (fig. 9, 120A) has an asymmetric shape.
Xu fails to explicitly disclose wherein the non-merged source/drain region has an asymmetric shape.
However Cho teaches wherein the non-merged source/drain region has an asymmetric shape [fig. 6, 150Ba].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the non-merged source/drain region to have an asymmetric shape to minimize parasitic capacitance.
Allowable Subject Matter
Claims 2-5, 7, & 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Xu/Cho/More teaches The method of claim 1, wherein the plurality of fin structures comprises:
a third fin structure that is located closer to the center of the semiconductor wafer relative to the second fin structure [Xu, annotated fig. 9];
wherein etching the plurality of fin structures results in formation of a third fin sidewall spacer [Xu, fig. 9, insulating spacer 141R, para 35] and a fourth fin sidewall spacer (Xu, fig. 9, 141R) on opposing sides of the third fin structure [Xu, annotated fig. 9]; and
wherein the method further comprises:
forming a non-merged source/drain region [Xu, fig. 9, source/drain region 120B, para 80] on the third fin structure [Xu, annotated fig. 9],
The prior art of record fails to explicitly disclose wherein the non-merged source/drain region is tilted toward the merged source/drain region as a result of a height of the fourth fin sidewall spacer being greater relative to a height of the third fin sidewall spacer.
Thereby claim 2 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 -5 contain allowable subject matter at least based upon their dependency on claim 2.
Regarding claim 7, Xu/Cho/More/Mao teaches The method of claim 6.
The prior art of record fails to explicitly disclose wherein the first power setting is greater relative to the second power setting, and
wherein the second non-zero bias voltage is greater relative to the first non-zero bias voltage.
Thereby claim 7 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12, Xu teaches The method of claim 8,
wherein the plurality of fin structures comprises
a third fin structure [annotated fig. 9], and wherein the method further comprises:
forming a non-merged source/drain region [annotated fig. 9, para 80 wherein the region comprises a silicon (Si) epitaxial layer –not a merge structure like 120A] on the third fin structure [annotated fig. 9].
The prior art of record fails to explicitly disclose wherein the non-merged source/drain region is tilted toward the merged source/drain region.
Thereby claim 12 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-15 contain allowable matter at least based upon their dependency on claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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