DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087,378. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 are anticipated by claims 1-20 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory bit cell comprising:
a stack of first transistors (claim 1, line 8); and
a second transistor configured to be activated based on a Y portion of an address, wherein a source/drain terminal of the second transistor is responsive to a common node that a source/drain terminal of one of the stack of first transistors is also responsive to (claim 1, lines 11-15).
Regarding claim 2, claim 2 of the patent recites the memory bit cell of claim 1, further comprising a logic gate configured to facilitate selection of the memory bit cell.
Regarding claim 3, claim 3 of the patent recites the memory bit cell of claim 2, wherein the logic gate comprises an AND gate or an NAND gate.
Regarding claim 4, claims 1 and 4 of the patent recite the memory bit cell of claim 2, further comprising a first word line configured to receive an X portion of the address and a second word line configured to receive the Y portion of the address, wherein the stack of first transistors comprises at least two transistors and a gate of a transistor of the stack of first transistors is coupled to a first input of the logic gate and the second word line is coupled to another input of the logic gate.
Regarding claim 5, claim 5 of the patent recites the memory bit cell of claim 2, wherein a gate of a transistor of the stack of first transistors is coupled to an output of the logic gate
Regarding claim 6, claim 6 of the patent recites the memory bit cell of claim 1, wherein at least one of the stack of first transistors is of a first type, the second transistor is of a second type, the first type is one of a P-type and an N-type, and the second type is the other of the P-type and the N-type.
Regarding claim 7, claim 7 of the patent recites a system comprising:
a memory bit cell comprising:
a first transistor (claim 7, a second transistor) responsive to a first word line and a second word line; and
a second transistor (claim 7, a third transistor) responsive to the first word line.
Regarding claim 8, claim 8 of the patent recites the system of claim 7, further comprising a logic gate configured to facilitate selection of the memory bit cell.
Regarding claim 9, claim 9 of the patent recites the system of claim 8, wherein the logic gate comprises an AND gate or an NAND gate.
Regarding claim 10, claim 10 of the patent recites the system of claim 8, wherein a gate of the second transistor is coupled to a first input of the logic gate and the second word line is coupled to another input of the logic gate.
Regarding claim 11, claim 11 of the patent recites the system of claim 8, wherein a gate of first transistor is coupled to an output of the logic gate.
Regarding claim 12, claim 7 and 12 of the patent recite the system of claim 7, further comprising a third transistor (claim 7, a first transistor) controlled by a bit line, wherein the third transistor is of a first type and at least one of the first and second transistors is of a second type, the first type is one of an N-type and a P-type, and the second type is the other of the N-type and the P-type.
Regarding claim 13, claim 13 of the patent recites the system of claim 7, further comprising:
a word line decoder; and
a word line level shifter coupled to the word line decoder and the first word line, wherein an X portion of an address is provided to the word line decoder.
Regarding claim 14, claims 7 and 14 of the patent recites the system of claim 7, further comprising:
a third transistor controlled by a bit line (claim 7, a first transistor);
a bit line decoder;
a bit line level shifter coupled to the bit line decoder, the bit line, and the second word line; and
a second word line level shifter coupled to the bit line decoder, the bit line, and the second word line, wherein a Y portion of an address is provided to the bit line decoder.
Regarding claim 15, claim 15 of the patent recites a method comprising:
activating a first word line based on decoding a first portion of an address;
activating a bit line and a second word line based on decoding a second portion of the address; and
activating a transistor of a bit cell based on the first word line and the second word line to program the bit cell based on a signal on the bit line.
Regarding claim 16, claim 16 of the patent recites the method of claim 15, wherein the bit cell includes a logic gate configured to facilitate selection thereof.
Regarding claim 17, claim 17 of the patent recites the method of claim 16, wherein the logic gate comprises an AND gate or a NAND gate.
Regarding claim 18, claim 18 of the patent recites the method of claim 16, wherein a gate of the transistor is coupled to an output of the logic gate.
Regarding claim 19, claim 19 of the patent recites the method of claim 15, wherein the transistor is a PMOS transistor or an NMOS transistor.
Regarding claim 20, claims 15 and 20 of the patent recite the method of claim 15, further comprising: providing the first portion of the address to a first decoder; providing the second portion of the address to a second decoder, wherein the first decoder is a word line decoder and the second decoder is a bit line decoder.
Claims 7-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-20 of U.S. Patent No. 11,664,081. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 7-20 are anticipated by claims 7-20 of the patent.
Regarding claim 7, claim 7 of the patent recites a system comprising:
a memory bit cell comprising:
a first transistor (claim 7, a second transistor) responsive to a first word line and a second word line; and
a second transistor (claim 7, a third transistor) responsive to the first word line.
Regarding claim 8, claim 8 of the patent recites the system of claim 7, further comprising a logic gate configured to facilitate selection of the memory bit cell.
Regarding claim 9, claim 9 of the patent recites the system of claim 8, wherein the logic gate comprises an AND gate or an NAND gate.
Regarding claim 10, claim 10 of the patent recites the system of claim 8, wherein a gate of the second transistor is coupled to a first input of the logic gate and the second word line is coupled to another input of the logic gate.
Regarding claim 11, claim 11 of the patent recites the system of claim 8, wherein a gate of first transistor is coupled to an output of the logic gate.
Regarding claim 12, claim 7 of the patent recite the system of claim 7, further comprising a third transistor (claim 7, a first transistor) controlled by a bit line, wherein the third transistor is of a first type and at least one of the first and second transistors is of a second type, the first type is one of an N-type and a P-type, and the second type is the other of the N-type and the P-type.
Regarding claim 13, claim 13 of the patent recites the system of claim 7, further comprising:
a word line decoder; and
a word line level shifter coupled to the word line decoder and the first word line, wherein an X portion of an address is provided to the word line decoder.
Regarding claim 14, claims 7 and 14 of the patent recites the system of claim 7, further comprising:
a third transistor controlled by a bit line (claim 7, a first transistor);
a bit line decoder;
a bit line level shifter coupled to the bit line decoder, the bit line, and the second word line; and
a second word line level shifter coupled to the bit line decoder, the bit line, and the second word line, wherein a Y portion of an address is provided to the bit line decoder.
Regarding claim 15, claim 15 of the patent recites a method comprising:
activating a first word line based on decoding a first portion of an address;
activating a bit line and a second word line based on decoding a second portion of the address; and
activating a transistor of a bit cell based on the first word line and the second word line to program the bit cell based on a signal on the bit line.
Regarding claim 16, claim 16 of the patent recites the method of claim 15, wherein the bit cell includes a logic gate configured to facilitate selection thereof.
Regarding claim 17, claim 17 of the patent recites the method of claim 16, wherein the logic gate comprises an AND gate or a NAND gate.
Regarding claim 18, claim 18 of the patent recites the method of claim 16, wherein a gate of the transistor is coupled to an output of the logic gate.
Regarding claim 19, claim 19 of the patent recites the method of claim 15, wherein the transistor is a PMOS transistor or an NMOS transistor.
Regarding claim 20, claims 15 and 20 of the patent recite the method of claim 15, further comprising: providing the first portion of the address to a first decoder; providing the second portion of the address to a second decoder, wherein the first decoder is a word line decoder and the second decoder is a bit line decoder.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 7 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai et al. (US 2021/0249601 hereinafter “Lai”).
Regarding claim 7, Lai (Fig. 5B) shows a system comprising:
a memory bit cell comprising:
a first transistor (M1) responsive to a first word line (WL1) and a second word line (WL2); and
a second transistor (M5) responsive to the first word line.
The first transistor M1 is connected in series with transistor M2; therefore, the voltage of WL2 provides a current to transistor M1 (transistor M1 is responsive to WL1 and WL2).
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827