DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Interconnection Structures Including a Resistor Device and a Dielectric Layer Comprising a Crystalline SiOC Based Material”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), Davis; Charles R. et al. (US 6486557; hereinafter Davis), Forbes; Leonard et al. (US 5886368; hereinafter Forbes), Shin; Hongsik et al. (US 2019/0229062; hereinafter Shin) and Liu; Xianzhou (US 2021/0028299; hereinafter Liu).
Regarding claim 1, Chen discloses an interconnection structure (refer to Fig 4; ¶ [0066-67]), comprising:
a first dielectric layer (126; Fig 4; ¶ [0057]) comprising a dielectric material (a low-K dielectric, for example; ¶ [0029,0034];
a first conductive layer (128; Fig 4; ¶ [0057]) disposed in the first dielectric layer;
a second dielectric layer (130; Fig 4; ¶ [0034]) disposed over the first dielectric layer; and
a resistor device (132; Fig 4; ¶ [0033]) disposed in the second dielectric layer.
Chen does not disclose:
(1) wherein the second dielectric layer comprises crystalline SiOC based material different from the dielectric material; and,
(2) wherein the resistor device comprises:
a first silicide blocking layer;
a first oxide layer disposed on the first silicide blocking layer;
a high resistance material layer disposed on the first oxide layer;
a second silicide blocking layer disposed on the high resistance material layer; and
a second oxide layer disposed on the second silicide blocking layer.
Regarding (1), in the same field of endeavor, Mignot disclose an interconnection structure
Including a first dielectric layer (114; Fig 1; ¶ [0030]) and a second dielectric layer (120; Fig 1; ¶ [0030]) which may comprise SiOC, SiCN or another of suitable ultra low k films well known in the art. Mignot does not disclose that a material of the second dielectric layer is different from a material of the first dielectric layer; however, it would have been obvious to a person having ordinary skill in the art that this may be the case for a variety of reasons including in order to manage competing device requirements, such as mechanical strength for structural integrity versus low permittivity (low k) for reducing parasitic capacitance. As one example, Davis discloses an interconnection structure (Fig 1; Col 2, line 61 – Col 3, line 34) having a first interconnection layer 18 comprising a first dielectric material 26 and a first conductive layer 28, and a second interconnection layer 20 comprising a second dielectric material 24 and a second conductive layer 22, wherein the second dielectric material 24 is different from first dielectric material 26, in order to place a low k material where most needed in the circuit while including a higher elastic modulus material elsewhere to improve structural integrity. (Col 1, lines 32-43, Col 2, lines 51-60).
Accordingly, it would have been obvious to a person having ordinary skill in the art from Mignon and Davis that the second dielectric layer of Chen may comprise SiOC based material different from the dielectric material of the first dielectric layer.
None of Chen, Mignon and Davis disclose the second dielectric layer comprising SiOC based material is crystalline SiOC based material; however, crystalline SiOC is known in the art: in the same field of endeavor, Forbes discloses a method of fabricating a transistor with crystalline silicon oxycarbide (SiOC) (microcrystalline or polycrystalline SiOC materials; Col 5; lines 44-53). Further, SiOC based materials encompass a range of materials known in the art and whose material properties, including heat conducting properties, vary according to their morphological state, among other things. Given the need to solve the problem of electromigration enhanced by high temperature with the on-going demand for reduced feature sizes (Chen; ¶ [0003,0036,0079]), it would have been at least obvious to try a crystalline form of SiOC based material to further improve thermal management in a semiconductor device having a resistive element (Chen; ¶ [0036]); See MPEP 2144.05). One would have had a reasonable expectation of success because the materials and structures are known in the art.
Regarding (2), in the same field of endeavor, Shin discloses a resistor device (comprising RS; Fig 6; ¶ [0016-52], disposed on a dielectric (153; Fig 6; ¶ [0035, 0049-52]) comprising:
an insulation layer (155a-155b; Fig 6; ¶ [0052-53]), comprising, for example, silicon nitride (¶ [0036, 0049]);
a first oxide layer (161, silicon oxide; Fig 6; ¶ [0037-38]) disposed on the insulation layer;
a high resistance material layer (163; Fig 6; ¶ [0037-39]) disposed on the first oxide layer,
a hardmask pattern, comprising, for example, silicon nitride (165; Fig 6; ¶ [0040]) disposed on the high resistance material layer; and
a second oxide layer (170, for example, silicon oxide having etch selectivity to the silicon nitride of 155; Fig 6; ¶ [0041-42]) disposed on the hardmask pattern.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the resistor device structure of Shin with the interconnection structure of Chen in view of Mignot, Davis, and Forbes. One would have been motivated to do this, in order to pattern the resistive structure and surrounding conductive lines and interconnection structure, without damage to the conductive lines, using appropriate materials to provide desired etch selectivity to achieve this (Shin; ¶ [0004-6, 0033-42, 0090-94]). One would have had a reasonable expectation of success because the resistor device structure is well known in the art, as is material and layer selection to achieve reliable manufacturing process integration of various components in a semiconductor device.
Shin does not disclose that the insulation layer and the hardmask pattern, comprising silicon nitride, are silicide blocking layers.
In the same field of endeavor, Liu discloses a silicide blocking layer comprising silicon nitride (silicide block layer 115; ¶ [0058]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the insulation layer and the hardmask pattern of Shin, comprising silicon nitride, are silicide blocking layers. One would have been motivated to come to this conclusion, with a reasonable expectation of success, in considering the material of Shin’s insulation layers and because the material is well known in the art as a silicide blocking layer.
Regarding claim 2, Chen in view of Mignot, Davis, Forbes, Shin, and Liu discloses the interconnection structure of claim 1, wherein the dielectric material is SiCN based material (as applied to claim 8, a dielectric material may comprise SiCN based material {Chen; ¶ [0029]; Mignot; ¶ [0030]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), Davis; Charles R. et al. (US 6486557; hereinafter Davis), Forbes; Leonard et al. (US 5886368; hereinafter Forbes), Shin; Hongsik et al. (US 2019/0229062; hereinafter Shin) and Liu; Xianzhou (US 2021/0028299; hereinafter Liu) and further in view of Watanabe; Kenji (US 2022/0045076; hereinafter Watanabe).
Regarding claim 3, Chen in view of Mignot, Davis, Forbes, Shin, and Liu discloses the interconnection structure of claim 1, wherein the dielectric material is a low-K dielectric, but does not disclose wherein the dielectric material is carbon doped Si3N4 or SiBCxNy.
In the same field of endeavor, Watanabe discloses SiBCxNy (SiBCN), SiOC and other materials as low-k dielectric materials which may alone or in combination comprise a low-k layer (¶ [0042]). Accordingly, it would have been obvious to a person having ordinary skill in the art that SiBCxNy may be used for the dielectric material. One would have been motivated to do this, with a reasonable expectation of success, as a suitable low-k dielectric material known in the art and for example in order to manage competing device requirements, such as mechanical strength for structural integrity versus low permittivity (low k) for reducing parasitic capacitance, as explained for claim 1.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), Davis; Charles R. et al. (US 6486557; hereinafter Davis), Forbes; Leonard et al. (US 5886368; hereinafter Forbes), Shin; Hongsik et al. (US 2019/0229062; hereinafter Shin) and Liu; Xianzhou (US 2021/0028299; hereinafter Liu) and further in view of Vannier; Patrick (US 2012/0153490; hereinafter Vannier).
Regarding claim 4, Chen in view of Mignot, Davis, Forbes, Shin, and Liu discloses the interconnection structure of claim 1, but does not disclose further comprising an etch stop layer disposed between the first dielectric layer and the second dielectric layer.
In the same field of endeavor, Vannier discloses an etch stop layer disposed between a first dielectric layer and a second dielectric layer (Abstr). Accordingly, it would have been obvious to a person having ordinary skill in the art to have included an etch stop layer according to claim 4. One would have been motivated to do this, with a reasonable expectation of success, in order to provide an etch selectivity between the first and second dielectrics, for example in order to etch holes in the second dielectric layer but not the first dielectric layer, to be filled with a conductive interconnection material, as is well known in the art.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), Davis; Charles R. et al. (US 6486557; hereinafter Davis), Forbes; Leonard et al. (US 5886368; hereinafter Forbes), Shin; Hongsik et al. (US 2019/0229062; hereinafter Shin) and Liu; Xianzhou (US 2021/0028299; hereinafter Liu) and further in view of Zhang; John Hongguang et al. (US 2012/0139114; hereinafter Zhang).
Regarding claim 5, Chen in view of Mignot, Davis, Forbes, Shin, and Liu discloses the interconnection structure of claim 1, but does not disclose further comprising a cap layer disposed on the first conductive layer, wherein the second dielectric layer is in direct contact with the first dielectric layer.
In the same field of endeavor, Zhang discloses a cap layer (260; Figs 2A-2C; ¶ [0013-14]) disposed on a first conductive layer (250; Figs 2A-2C; ¶ [0013-14]) in a first dielectric layer (210; Figs 2A-2C; ¶ [0013-14]). Because the cap layer does not extend across first dielectric layer 210, when another dielectric layer (of another metallization layer 205; ¶ [0013]) is disposed over the first dielectric layer, the second dielectric layer will be in direct contact with the first dielectric layer. Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the cap layer of Zhang with the interconnection structure of claim 1 and satisfy the further limitation of claim 5. One would have been motivated to do this in order to improve reliability of the interconnection structure (Zhang; BEOL reliability, ¶ [0002,0018]). One would have had a reasonable expectation of success because the same material (copper; Chen; ¶ [0028]); Zhang; ¶ [0018]) is disclosed for the first conductive layers of Chen and Zhang, and because such a cap layer is well known in the art.
Regarding claim 6, Chen in view of Mignot, Davis, Forbes, Shin, and Liu, and further in view of Zhang discloses the interconnection structure of claim 5, wherein the cap layer (Zhang; 260; Figs 2A-2C) comprises graphene (Zhang; ¶ [0013-14]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), Davis; Charles R. et al. (US 6486557; hereinafter Davis), Forbes; Leonard et al. (US 5886368; hereinafter Forbes), Shin; Hongsik et al. (US 2019/0229062; hereinafter Shin) and Liu; Xianzhou (US 2021/0028299; hereinafter Liu), further in view of Zhang; John Hongguang et al. (US 2012/0139114; hereinafter Zhang), and still further in view of Horak; David V. et al. (US 2011/0272812; hereinafter Horak).
Regarding claim 7, Chen in view of Mignot, Davis, Forbes, Shin, and Liu, and further in view of Zhang discloses the interconnection structure of claim 5, but does not disclose wherein the cap layer comprises silicon nitride.
In the same field of endeavor, Horak discloses an interconnect structure having a cap layer (35; Fig 3; ¶ [0013-15]) comprising silicon nitride, where the cap layer is selectively deposited only on a conductive layer (32; Fig 2; ¶ [0013]). Accordingly, it would have been obvious to have substituted the silicon nitride cap of Horak for the graphene cap of claim 5. One would have been motivated to do this, at least as an alternate material and/or to provide a copper diffusion barrier and/or oxygen diffusion barrier and to ensure good electromigration performance (Horak; ¶ [0001]). One would have had a reasonable expectation of success because of the similar conductive layer material disclosed by Chen, Zhang and Horak.
Claims 8 , 11-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), and Forbes; Leonard et al. (US 5886368; hereinafter Forbes).
Regarding claim 8, Chen discloses an interconnection structure (refer to Fig 4; ¶ [0066-67]), comprising:
a first dielectric layer (122; Fig 4; ¶ [0057]);
a first conductive layer (124; Fig 4; ¶ [0057]) disposed in the first dielectric layer;
a second dielectric layer (126; Fig 4; ¶ [0057]) disposed over the first dielectric layer;
a second conductive layer (128; Fig 4; ¶ [0057]) disposed in the second dielectric layer in electrical contact with the first conductive layer (through via 302; Fig 4; ¶ [0064]);
a third dielectric layer (130; Fig 4; ¶ [0034]) disposed over the second dielectric layer, wherein the third dielectric layer comprises crystalline SiOC based material; and
a resistor device (132; Fig 4; ¶ [0033]) disposed in the third dielectric layer.
Chen does not disclose wherein the third dielectric layer comprises crystalline SiOC based material.
In the same field of endeavor, Mignot disclose an interconnection structure including a first dielectric layer (106; Fig 1; ¶ [0030]), a second dielectric layer (114; Fig 1; ¶ [0030]), and a third dielectric layer (120; Fig 1; ¶ [0030]), which may each comprise SiOC or SiCN. Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have used the SiOC of Mignot for the third dielectric layer of Chen. One would have been motivated to do this, with a reasonable expectation of success, because it is a well known and suitable material for use as an interconnection dielectric.
Neither Mignon nor Chen disclose the third dielectric layer comprising SiOC based material is crystalline SiOC based material; however, crystalline SiOC is known in the art:
In the same field of endeavor, Forbes discloses a method of fabricating a transistor with crystalline silicon oxycarbide (SiOC) (microcrystalline or polycrystalline SiOC materials; Col 5; lines 44-53). Further, SiOC based materials encompass a range of materials known in the art and whose material properties, including heat conducting properties, vary according to their morphological state, among other things. Given the need to solve the problem of electromigration enhanced by high temperature (due to the resistor device; Chen; ¶ [0036]) with the on-going demand for reduced feature sizes (Chen; ¶ [0003,0036,0079]), it would have been at least obvious to try a crystalline form of SiOC based material to further improve thermal management in a semiconductor device having a resistive element (Chen; ¶ [0036]); See MPEP 2144.05). One would have had a reasonable expectation of success because the materials and structures are known in the art.
Regarding claim 11, Chen in view of Mignot and Forbes discloses the interconnection structure of claim 8, wherein the first dielectric layer and the second dielectric layer comprise SiCN based material (as applied to claim 8, suitable materials of Chen in view of Mignot for the first dielectric layer and the second dielectric layer may comprise SiCN based material, and it would have been obvious to select a combination from among the suitable materials {Chen; ¶ [0029]; Mignot; ¶ [0030])} for the first, second and third dielectric layers, which in combination provide at least adequate results in regards to the heat dissipation requirements from the resistor device (Chen; ¶ [0036]).
Regarding claim 12, Chen in view of Mignot and Forbes discloses the interconnection structure of claim 8, wherein the first dielectric layer and the second dielectric layer comprise crystalline SiOC based material (as applied to claim 8, suitable materials for the first, second, and third dielectric layers may comprise crystalline SiOC based material, and it would have been obvious to select from among the suitable materials {Chen; ¶ [0029]; Mignot; ¶ [0030]); in view of Forbes as applied to claim 8} for each of the first, second and third dielectric layers, the material(s) which provide at least adequate results in regards to the heat dissipation requirements from the resistor device (Chen; ¶ [0036]).
Regarding claim 15, Chen in view of Mignot and Forbes discloses the interconnection structure of claim 8, wherein the resistor device comprises a high-resistance layer (Chen; titanium nitride, or tantalum nitride, for example; ¶ [0033]) covered by at least one dielectric layer (Chen; 134; Fig 4; ¶ [0035]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), and Forbes; Leonard et al. (US 5886368; hereinafter Forbes), and further in view of Vannier; Patrick (US 2012/0153490; hereinafter Vannier).
Regarding claim 13, Chen in view of Mignot and Forbes discloses the interconnection structure of claim 8, but does not disclose wherein the second dielectric layer and the first dielectric layer are separated by a first etch stop layer, and the third dielectric layer and the second dielectric layer are separated by a second etch stop layer.
In the same field of endeavor, Vannier discloses an etch stop layer disposed between a first dielectric layer and a second dielectric layer (Abstr). Accordingly, it would have been obvious to a person having ordinary skill in the art to have included an etch stop layer according to claim 13. One would have been motivated to do this, with a reasonable expectation of success, in order to provide an etch selectivity between the first and second dielectrics, for example in order to etch holes in the second dielectric layer but not the first dielectric layer, to be filled with a conductive interconnection material, as is well known in the art.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Mignot; Yann et al. (US 2020/0388567; hereinafter Mignot), and Forbes; Leonard et al. (US 5886368; hereinafter Forbes), and further in view of Zhang; John Hongguang et al. (US 2012/0139114; hereinafter Zhang).
Regarding claim 14, Chen in view of Mignot and Forbes discloses the interconnection structure of claim 8, but does not disclose wherein further comprising: a first cap layer disposed on the first conductive layer; and a second cap layer disposed on the second conductive layer, wherein the second dielectric layer is in direct contact with the first dielectric layer, and the third dielectric layer is in direct contact with the second dielectric layer.
In the same field of endeavor, Zhang discloses a cap layer (260; Figs 2A-2C; ¶ [0013-14]) disposed on a first conductive layer (250; Figs 2A-2C; ¶ [0013-14]) in a first dielectric layer (210; Figs 2A-2C; ¶ [0013-14]). Because the cap layer does not extend across first dielectric layer 210, when another dielectric layer (of another metallization layer 205; ¶ [0013]) is disposed over the first dielectric layer, the second dielectric layer will be in direct contact with the first dielectric layer. Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the cap layer of Zhang with the interconnection structure of claim 8 and satisfy the further limitation of claim 14. One would have been motivated to do this in order to improve reliability of the interconnection structure (Zhang; BEOL reliability, ¶ [0002,0018]). One would have had a reasonable expectation of success because the same material (copper; Chen; ¶ [0028]); Zhang; ¶ [0018]) is disclosed for the first conductive layers of Chen and Zhang, and because such a cap layer is well known in the art.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Watanabe; Kenji (US 2022/0045076; hereinafter Watanabe); Forbes; Leonard et al. (US 5886368; hereinafter Forbes), and Jerome; Rick Carlton et al. (US 2022/0271118; hereinafter Jerome).
Regarding claim 16, Chen discloses an interconnection structure (refer to Fig 4; ¶ [0066-67]), comprising:
a first dielectric layer (126; Fig 4; ¶ [0057]; comprising a low-K dielectric, for example; ¶ [0039,0029]);
a first conductive layer (128; Fig 4; ¶ [0057]) disposed in the first dielectric layer;
a second dielectric layer (130, comprising a low-K dielectric, for example; Fig 4; ¶ [0034,0029]) disposed over the first dielectric layer; and
a resistor device (132; Fig 4; ¶ [0033]) disposed in the second dielectric layer, wherein the resistor device comprises: a high resistance material layer (titanium nitride or tantalum nitride; ¶ [0033]).
Chen does not disclose:
(1) the first dielectric layer comprises carbon doped Si3N4 or SiBCxNy;
(2) the second dielectric layer comprises crystalline SiOC based material; and
(3) the resistor device comprises: a first oxide layer, wherein the high resistance material layer is disposed over the first oxide layer, and a second oxide layer disposed over the high resistance material layer.
Regarding (1) and (2), in the same field of endeavor, Watanabe discloses SiBCxNy (SiBCN), SiOC and other materials as low-k dielectric materials which may alone or in combination comprise a low-k layer (¶ [0042]). Accordingly, it would have been obvious to a person having ordinary skill in the art that these materials may be used in the interconnection structure of Chen, either alone or in combination for each of the first dielectric layer and the second dielectric layer; that is the first dielectric layer of Chen may comprise SiBCxNy and the second dielectric layer of Chen may comprise SiOC based material, as two materials selected from a group of low-k dielectric materials known in the art.
Neither Chen or Watanabe disclose the second dielectric layer comprising SiOC based material is crystalline SiOC based material; however, crystalline SiOC is known in the art: in the same field of endeavor, Forbes discloses a method of fabricating a transistor with crystalline silicon oxycarbide (SiOC) (microcrystalline or polycrystalline SiOC materials; Col 5; lines 44-53). Further, SiOC based materials encompass a range of materials known in the art and whose material properties, including heat conducting properties, vary according to their morphological state, among other things. Given the need to solve the problem of electromigration enhanced by high temperature with the on-going demand for reduced feature sizes (Chen; ¶ [0003,0036,0079]), it would have been at least obvious to try a crystalline form of SiOC based material to further improve thermal management in a semiconductor device having a resistive element (Chen; ¶ [0036]); See MPEP 2144.05). One would have had a reasonable expectation of success because the materials and structures are known in the art.
Regarding (3), in the same field of endeavor, Jerome discloses a back-end resistor device (Fig 4) comprising a first oxide layer (14; Fig 4; ¶ [0025]), wherein a high resistance material layer (15; Fig 4; ¶ [0025]) is disposed over the first oxide layer, and a second oxide layer (17; Fig 4; ¶ [0025-26] disposed over the high resistance material layer. It would have been obvious for a person having ordinary skill in the art to have combined the resistor structure taught by Jerome with the interconnection structure of Chen in view of Watanabe and Forbes. One would have been motivated to do this in order to protect the high resistance material layer from exposure to etchants that may be used in the further manufacturing of the interconnection structure (Jerome; ¶ [0018]), and would have had a similar expectation of success because of the similar placement of the resistor device in an interconnection structure by each of Jerome and Chen.
Regarding claim 17, Chen in view of Watanabe, Forbes, and Jerome discloses the interconnection structure of claim 16, wherein the high resistance material layer comprises TiN or TaN (as applied to claim 16).
Regarding claim 18, Chen in view of Watanabe, Forbes, and Jerome discloses the interconnection structure of claim 17, wherein the first (Jerome; ¶ [0070]) and second oxide layers (Jerome; ¶ [0026]) each comprises silicon oxide.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Watanabe; Kenji (US 2022/0045076; hereinafter Watanabe); Forbes; Leonard et al. (US 5886368; hereinafter Forbes), and Jerome; Rick Carlton et al. (US 2022/0271118; hereinafter Jerome), and further in view of Vannier; Patrick (US 2012/0153490; hereinafter Vannier).
Regarding claim 19, Chen in view of Watanabe, Forbes, and Jerome discloses the interconnection structure of claim 16, but does not disclose further comprising an etch stop layer disposed between the first dielectric layer and the second dielectric layer.
In the same field of endeavor, Vannier discloses an etch stop layer disposed between a first dielectric layer and a second dielectric layer (Abstr). Accordingly, it would have been obvious to a person having ordinary skill in the art to have included an etch stop layer according to claim 19. One would have been motivated to do this, with a reasonable expectation of success, in order to provide an etch selectivity between the first and second dielectrics, for example in order to etch holes in the second dielectric layer but not the first dielectric layer, to be filled with a conductive interconnection material, as is well known in the art.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Wan-Te et al. (US 2018/0337125; hereinafter Chen) in view of Watanabe; Kenji (US 2022/0045076; hereinafter Watanabe); Forbes; Leonard et al. (US 5886368; hereinafter Forbes), and Jerome; Rick Carlton et al. (US 2022/0271118; hereinafter Jerome), and further in view of Zhang; John Hongguang et al. (US 2012/0139114; hereinafter Zhang).
Regarding claim 20, Chen in view of Watanabe, Forbes, and Jerome discloses the interconnection structure of claim 16, but does not disclose further comprising a cap layer disposed on the first conductive layer, wherein the second dielectric layer is in direct contact with the first dielectric layer.
In the same field of endeavor, Zhang discloses a cap layer (260; Figs 2A-2C; ¶ [0013-14]) disposed on a first conductive layer (250; Figs 2A-2C; ¶ [0013-14]) in a first dielectric layer (210; Figs 2A-2C; ¶ [0013-14]). Because the cap layer does not extend across first dielectric layer 210, when another dielectric layer (of another metallization layer 205; ¶ [0013]) is disposed over the first dielectric layer, the second dielectric layer will be in direct contact with the first dielectric layer. Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the cap layer of Zhang with the interconnection structure of claim 16. One would have been motivated to do this in order to improve reliability of the interconnection structure (Zhang; BEOL reliability, ¶ [0002,0018]). One would have had a reasonable expectation of success because the same material (copper; Chen; ¶ [0028]); Zhang; ¶ [0018]) is disclosed for the first conductive layers of Chen and Zhang, and because such a cap layer is well known in the art.
Allowable Subject Matter
Claims 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein a thermal conductivity of the third dielectric layer is between 5 W/mK and 500 W/mK”, along with the additional limitations of Claim 8 including “wherein the third dielectric layer comprises crystalline SiOC based material”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Stabler C, Ionescu E, Graczyk-Zajac M, Gonzalo-Juan I, Riedel R. Silicon oxycarbide glasses and glass-ceramics: “All-Rounder” materials for advanced structural and functional applications. J Am Ceram Soc. 2018; 101: 4817–4856. https://doi.org/10.1111/jace.15932
Gurlo, A., Ionescu, E., Riedel, R. and Clarke, D.R. (2016), The Thermal Conductivity of Polymer-Derived Amorphous Si–O–C Compounds and Nano-Composites. J. Am. Ceram. Soc., 99: 281-285. https://doi.org/10.1111/jace.13947
Rodrigo Martins, Manuela Vieira, Isabel Ferreira, Elvira Fortunato, Leopoldo Guimara˜es, Transport properties of doped silicon oxycarbide microcrystalline films produced by spatial separation techniques, Solar Energy Materials and Solar Cells, Volumes 41–42, 1996, Pages 493-517, ISSN 0927-0248, https://doi.org/10.1016/0927-0248(95)00096-8
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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