DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/18/2025 and 07/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 9-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2020/0044087 to Guha et al (hereinafter Guha) in view of US PG Pub 2020/0135922 to Chen et al (hereinafter Chen).
Regarding Claim 1, Guha discloses a semiconductor structure, comprising:
an active region comprising a channel region (312, Fig. 14A) and source/drain region (360);
a gate structure (336) wrapping over the channel region;
a cap layer disposed on the gate structure (see below);
a multilayer gate spacer (332; [0056] multilayer structure) disposed along sidewalls of the gate structure and sidewalls of the cap layer; and
a source/drain feature (360) disposed over the source/drain region,
wherein the multilayer gate spacer comprises a low-k dielectric layer in contact with the sidewall of the gate structure and a silicon sublayer over the low-k dielectric layer ([0056] numerous low-k dielectric materials and silicon based layers are listed as options for the multilayer gate spacer).
Guha does not disclose a cap layer disposed on the gate structure.
Chen discloses a gate structure (342a, Fig. 10) having a gate cap layer (343) and sidewalls (344a) that extend to cover both the gate structure and the cap layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the semiconductor structure of Guha to have included a cap layer over the gate structure. Gate caps were known in the art for providing isolation from parasitic capacitance with overlying metallization layers and protection to the gate electrode from future manufacturing steps.
Regarding Claim 2, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 1, wherein the cap layer comprises silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, or hafnium oxide (Chen [0023]).
Regarding Claim 3, the combination of Guha and Frougier makes obvious the semiconductor structure of Claim 1, wherein the low-k dielectric layer comprises silicon oxide, porous silicon oxide, silicon oxycarbonitride, fluorinated silica glass (FSG), carbon doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes, or polyimide (Guha, [0056]).
Regarding Claim 4, the combination of Guha and Frougier makes obvious the semiconductor structure of claim 1, wherein the silicon sublayer comprises silicon (Guha [0056]).
Regarding Claim 9, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 1,
wherein the gate structure comprises a gate dielectric layer (334, Fig. 14A) and a gate electrode (336) layer over the gate dielectric layer, and
wherein the cap layer is in contact with top surfaces of the gate electrode layer and the gate dielectric layer (Chen, Fig. 10).
Regarding Claim 10, Guha discloses a semiconductor structure, comprising:
an active region comprising a channel region (Fig. 14A, 312) and source/drain region (360);
a gate structure (336) wrapping over the channel region;
a cap layer disposed on the gate structure (see below);
a multilayer gate spacer (332; [0056] multilayer structure) disposed along sidewalls of the gate structure and sidewalls of the cap layer;
a source/drain feature (360) disposed over the source/drain region;
a contact etch stop layer (CESL) (370) disposed along sidewalls of the multilayer gate spacer and on a top surface of the source/drain feature;
a first interlayer dielectric (ILD) layer (370, Fig. 9A) disposed over the CESL; and
a second ILD layer (not pictured, see below) disposed over top surfaces of the CESL, the first ILD layer, the multilayer gate spacer, and the cap layer,
wherein the multilayer gate spacer comprises a low-k dielectric layer in contact with the sidewall of the gate structure and a silicon sublayer over the low-k dielectric layer ([0056] numerous low-k dielectric materials and silicon based layers are listed as options for the multilayer gate spacer).
Guha does not disclose a cap layer disposed on the gate structure.
Chen discloses a gate structure (342a, Fig. 10) having a gate cap layer (343) and sidewalls (344a) that extend to cover both the gate structure and the cap layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the semiconductor structure of Guha to have included a cap layer over the gate structure. Gate caps were known in the art for providing isolation from parasitic capacitance with overlying metallization layers and protection to the gate electrode from future manufacturing steps. Furthermore, while not disclosed by the references, additional dielectric or ILD layers placed above the semiconductor device suggested by the references would have been obvious to allow for additional metallization layers to connect the device to a circuit and to insulate the device from electrical or environmental effects.
Regarding Claim 11, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 10, wherein the silicon sublayer comprises silicon (Guha [0056])
Regarding Claim 14, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 10, wherein the top surfaces of the CESL, the first ILD layer, the multilayer gate spacer, and the cap layer are coplanar (Guha, Figs. 9A & 14A and Chen Fig. 10).
Regarding Claim 15, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 10, further comprising:
a source/drain contact (Guha, 390, Fig. 14A) extending through the second ILD layer, the first ILD layer, and the CESL to electrically couple to the source/drain feature by way of a silicide layer (Guha, [0079] contact resistance reducing layer).
Regarding Claim 16, the combination of Guha and Chen makes obvious the semiconductor structure of Claim 15,
wherein the source/drain contact comprises titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN) (Guha [0079]), and
wherein the silicide layer comprises titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi) (the adhesion layers of Guha satisfy these material requirements [0079]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 5-8, 12, 13 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 12,148,813. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences in claim language do not provide for a structure non-obvious from the cited patent.
Pending Claim 5 requires the semiconductor structure of Claim 1 further comprise:
a contact etch stop layer (CESL) disposed along sidewalls of the multilayer gate spacer and on a top surface of the source/drain feature, wherein the CESL comprises at least one silicon sublayer and at least one nitrogen-containing sublayer.
If written into independent for with all of Claim 1’s limitations, the differences in the pending application and the cited patent are a rewarding of the fin to instead be an active region and the inclusion of a cap layer for the gate structure. Since Applicant requires the gate structure to be a Gate-All-Around structure, it would have been obvious for the active region to comprise a fin. As noted above, the inclusion of a gate cap layer is obvious to provide protection and insulation to the gate structure. The inclusion or removal of the gate cap layer does not provide patentable distinction.
Claims 6-8 depend on Claim 5 and their limitations can be found in patented Claims 1 and 4.
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Claim 12 results in a structure similar to Claim 5 and is rejected in view of patented Claim 1.
Claim 13 depends on Claim 12 and it’s limitations can be found in patented Claim 4.
Pending Claim 17 is rejected in view of patented Claims 1 and 8. It differs from the resulting structure claimed by Claim 8 similarly to Claim 5.
Claims 18-20 depend on Claim 17 and their limitations can be found in Claims 4 and 9 or are otherwise an obvious result of planarization.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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