DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 9-10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. US 20200220018 A1 (hereinafter referred to as Jang).
Regarding claim 1, Jang teaches
A method (method of forming “semiconductor device 100” para. 0021 FIG. 2) comprising:
forming a set of nanostructures (“channel structures 140” para. 0022) on a substrate (“substrate 101” and “active region 105”, para. 0022), wherein each nanostructure of the set of nanostructures comprises a channel region (“channel structures 140” are channels);
forming a recess (“a portion of the active region 105 on the substrate 101 may be recessed” as shown in FIG. 2-3, para. 0026) in the substrate adjacent the set of nanostructures;
forming a first epitaxial region (“second layer 152B”, epitaxially grown, para. 0030, 0032) in the recess using a first epitaxial growth process, wherein the first epitaxial region fills the recess (“second layer 152B” at least partially fills the recess in “active region 105”);
forming a second epitaxial region (“second epitaxial layer 154” para. 0033) on the first epitaxial region using a second epitaxial growth process that is different from the first epitaxial growth process (“second epitaxial layer 154” may be grown from the “first epitaxial layers 152” and has a different composition, such that it is understood to be a different epitaxial growth process, para. 0034); and
forming a gate structure (“gate structure 160” para. 0022) on the set of nanostructures, wherein the gate structure surrounds the channel region of each nanostructure of the set of nanostructures (“gate structure 160” surrounds “channel structures 140” as shown in FIG. 2).
Regarding claim 2, Jang teaches the method of claim 1, wherein the first epitaxial growth process forms sidewall epitaxial regions (“first layers 152A” para. 0030) on sidewalls of the nanostructures of the set of nanostructures.
Regarding claim 5, Jang teaches the method of claim 1, wherein the first epitaxial region has a lower concentration of impurities than the second epitaxial region (“concentration of impurities included in the first epitaxial layer 152 may be within a range of approximately 2×10.sup.20/cm.sup.3 to 8×10.sup.20/cm.sup.3” para. 0032, while “concentration of impurities included in the second epitaxial layer 154 may be within a range of approximately 3.1×10.sup.21/cm.sup.3to 3.9×10.sup.21/cm.sup.3” para. 0034).
Regarding claim 9, Jang teaches
A method (method of forming “semiconductor device 100” para. 0021 FIG. 2) comprising:
forming a nanostructure (“channel structure 140” para. 0022) over a fin, wherein the nanostructure comprises a first semiconductor material (silicon, germanium, or silicon-germanium, para. 0028);
etching a recess (“a portion of the active region 105 on the substrate 101 may be recessed” para. 0026) in the fin adjacent the nanostructure;
epitaxially depositing a second semiconductor material (“first epitaxial layers 152” para. 0030) in the recess (“second layer 152B” para. 0030) and on a sidewall (“first layers 152A” para. 0030) of the nanostructure;
epitaxially depositing a third semiconductor material (“second epitaxial layer 154” para. 0034) on the second semiconductor material and over the sidewall of the nanostructure (“second epitaxial layer 154 may surround a surface of the first epitaxial layer 152 on which the first epitaxial layer 152 is not in contact with the channel structure 140 or the active region 105” para. 0033); and
forming a gate stack (“gate structure 160” para. 0022) on the nanostructure.
Regarding claim 10, Jang teaches the method of claim 9, wherein the second semiconductor material in the recess extends above a top surface of the fin (“the second layer 152B may have a second maximum thickness T2 from an upper surface of the active region 105” as is shown in FIG. 3 as extending past the top surface of “active region 105”, para. 0046).
Regarding claim 12, Jang teaches the method of claim 9, wherein the second semiconductor material in the recess is physically separated from the second semiconductor material on the sidewall of the nanostructure (“first layers 152A may be separated from the second layer 152B” para. 0030).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 9 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. US 20220285511 A1 (hereinafter referred to as Park).
Regarding claim 1, Park teaches
A method (method of forming “semiconductor device 100” para. 0023 FIG. 2A and 11A-11K) comprising:
forming a set of nanostructures (“channel structures 140” para. 0023) on a substrate (“substrate 101” with “active regions 105”, para. 0023), wherein each nanostructure of the set of nanostructures comprises a channel region (“cannel structures 140” are channels);
forming a recess (“recess regions RC” in “active regions 105”, para. 0027 FIG. 11D) in the substrate adjacent the set of nanostructures;
forming a first epitaxial region (“preliminary first epitaxial layer 152P” in “third region R3”, para. 0100 FIG. 11E) in the recess using a first epitaxial growth process, wherein the first epitaxial region fills the recess (“preliminary first epitaxial layer 152P” fills “recess region RC” in “third region R3”);
forming a second epitaxial region (“second epitaxial layer 154C” para. 0106 FIG. 11G) on the first epitaxial region using a second epitaxial growth process that is different from the first epitaxial growth process (“second epitaxial layer 154C” is formed during a separate deposition process, para. 0106-0108); and
forming a gate structure (“gate structures 160” para. 0113 FIG. 11I) on the set of nanostructures, wherein the gate structure surrounds the channel region of each nanostructure of the set of nanostructures (“gate structures 160” are formed around “channel structures 140”, para. 0113).
Regarding claim 3, Park teaches the method of claim 2 further comprising performing an etching process to remove the sidewall epitaxial regions (“preliminary first epitaxial layers 152P may be removed to have different depths in the first to fourth regions R1, R2, R3, and R4 to form first to fourth additional recess regions AR1, AR2, AR3, and AR4, respectively”, para. 0104 FIG. 11F. In “third region R3” sidewall portions of upper region “preliminary first epitaxial layer 152P” are removed).
Regarding claim 6, Park teaches the method of claim 1, wherein the first epitaxial region is n-type and the second epitaxial region is p-type (for a pFET, “first epitaxial layer 15C”, which is formed from “preliminary first epitaxual layer 152P”, is n-type and “second epitaxial layer 152C” is p-type, para. 0040)
Regarding claim 9, Park teaches
A method (method of forming “semiconductor device 100” para. 0023 FIG. 2A and 11A-11K) comprising:
forming a nanostructure (“channel layer 142” in “region R3”, para. 0023) over a fin, wherein the nanostructure comprises a first semiconductor material (“channel layer 142” comprises silicon, para. 0029);
etching a recess (“recess regions RC” in “third region R3”, para. 0027 FIG. 11D) in the fin adjacent the nanostructure;
epitaxially depositing a second semiconductor material in the recess (“preliminary first epitaxial layer 152P” in “third region R3”, para. 0100 FIG. 11E) and on a sidewall of the nanostructure (“preliminary first epitaxial layer 152P” in “third region R3” contacts the sidewall of “channel layer 142”);
epitaxially depositing a third semiconductor material (“second epitaxial layer 154C” para. 0106 FIG. 11G) on the second semiconductor material and over the sidewall of the nanostructure; and
forming a gate stack (“gate structures 160” para. 0113 FIG. 11I) on the nanostructure.
Regarding claim 11, Park teaches the method of claim 9 further comprising etching the second semiconductor material to expose the sidewall of the nanostructure (“preliminary first epitaxial layers 152P may be removed to have different depths in the first to fourth regions R1, R2, R3, and R4 to form first to fourth additional recess regions AR1, AR2, AR3, and AR4, respectively”, para. 0104 FIG. 11F. In “third region R3” sidewall portions of upper region “preliminary first epitaxial layer 152P” are removed).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 1 above
Regarding claim 8, Jang taches the method of claim 1, wherein a top surface of the first epitaxial region is below the set of nanostructures.
Nevertheless, FIG. 3 suggests that “second layer 152B” is below “channel layer 141”. Furthermore, the examiner understands that the condition that “second layer 152B” have a larger thickness than “first layer 152A” may be satisfied in cases where “second layer 152B” extends past or is below “channel layer 141” (para. 0031). Also, the lower surface of “source/drain region 150” may have different shapes and depths (para. 0031). The doping profile is controlled by the thicknesses of the elements of “first epitaxial layer 152”, as shown in FIG. 4A-5B (para. 0047-0055). The examiner understands that changes to the doping profile will affect the electrical performance of the “source/drain region 150”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the shape of the “source/drain region 150”, including depth and by consequence the “second layer 152b”, is a result affective variable that leads to desired doping profile and electrical properties.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape and size of the first epitaxial region. The extent of the first epitaxial region may impart desired electrical properties due to the change in doping profile of the source/drain region.
Regarding claim 16, Jang teaches the method of claim 9, wherein the recess has a depth in the range of 1 nm to 50 nm.
Nevertheless, FIG. 3 suggests that “second layer 152B” is below “channel layer 141”. Furthermore, the examiner understands that the condition that “second layer 152B” have a larger thickness than “first layer 152A” may be satisfied in cases where “second layer 152B” extends past or is below “channel layer 141” (para. 0031). Also, the lower surface of “source/drain region 150” may have different shapes and depths (para. 0031). The doping profile is controlled by the thicknesses of the elements of “first epitaxial layer 152”, as shown in FIG. 4A-5B (para. 0047-0055). The examiner understands that changes to the doping profile will affect the electrical performance of the “source/drain region 150”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the shape of the lower surface of “source/drain region 150”, and therefore the depth the “second layer 152b”, is a result affective variable that leads to desired doping profile and electrical properties.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape and size of the first epitaxial region. The extent of the first epitaxial region may impart desired electrical properties due to the change in doping profile of the source/drain region.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 2 above, in view of Bentley et al. US 20170317169 A1 (hereinafter referred to as Bentley).
Regarding claim 4, Jang teaches the method of claim 2 but fails to teach wherein the sidewall epitaxial regions have facets.
Nevertheless, Bentley teaches
wherein the sidewall epitaxial regions have facets (“source/drain material 190” are shown having triangular cross sections and thus have two facets, para. 0043 FIG. 1F).
Jang and Bentley teach finfet devices. The “first epitaxial layers 152” in the recess and the sidewalls of “channel structures 140” in Jang have rounded surfaces while the “source/drain material 190” in Bentley have polygonal shapes. Both features are formed by epitaxial growth. Following MPEP 2143.III.B, the shape of the sidewall epitaxial regions are a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed sidewall epitaxial regions was significant.
Regarding claim 14, Jang teaches the method of claim 9, wherein the recess has a triangular cross-section.
Nevertheless, Bentley teaches
wherein the sidewall epitaxial regions have facets (“source/drain material 190” are shown having triangular cross sections and thus have two facets, para. 0043 FIG. 1F).
Jang and Bentley teach finfet devices. The “first epitaxial layers 152” in the recess and the sidewalls of “channel structures 140” in Jang have rounded surfaces while the “source/drain material 190” in Bentley have polygonal shapes. Both features are formed by epitaxial growth. Following MPEP 2143.III.B, the shape of the sidewall epitaxial regions are a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed sidewall epitaxial regions was significant.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 9, in view of Balakrishnan et al. US 20180083113 A1 (hereinafter referred to as Balakirshnan), and in view of Cheng et al. US 20210210598 A1 (hereinafter referred to as Cheng).
Jang teaches the method of claim 9 but fails to teach further comprising etching the sidewall of the nanostructure, wherein the sidewall of the nanostructure has a different profile after the etching.
Nevertheless, Balakrishnan teaches
etching the sidewall of the nanostructure (“portion of the nano-sheet channel layers 140 can be removed using a selective isotropic etch” para. 0077 FIG. 10-12).
Jang and Balakrishnan teach finfets with nanostructures. The “nanosheet channel layers 140” in the two cut-stacks have different lengths; one stack has longer length “nanosheet channel layers 140” in one stack are longer for devices with lower leakage current while the other stack has shorter length “nanosheet channel layers 140” for faster devices (para. 0086 FIG. 12). The length of the “nanosheet channel layers 140” affects the device performance. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “channel structures 140” can be etched to adjust their channel length, and thus their electrical performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Jang with the etching of the nanostructure sidewall as taught in Balakrishnan. Etching of the nanostructure sidewalls adjusts their length and the device performance.
However, Jang, modified by Balakrishnan, fail to teach wherein the sidewall of the nanostructure has a different profile after the etching.
Nevertheless, Cheng teaches
wherein the sidewall of the nanostructure has a different profile after the etching (“silicon channel nanosheets 108 are subjected to an etch process” such that “channel recesses 118” are crescent or half-moon shaped with each defining a depth “D2”, para. 0042 FIG. 6).
Jang, modified by Balakrishnan, and Cheng teach finFET devices with nanostructures. The etching in Cheng produces curved sidewalls of “silicon channel nanosheets 108” and the examiner understands this may be due to the type of etching process. Furthermore, the examiner understands that the curved surface area of the sidewall of “silicon channel nanosheets 108” is greater than if they were flat. The current density passing at the interface of the curved sidewalls may be reduced for a same total current passing through if sidewalls were flat. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the profile of the sidewalls of “channel structures 140” is determined by the etching process and a crescent-shape sidewall will have greater surface area in contact with the “source/drain region 150”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Jang and Balakrishnan with the etching process taught in Cheng. The sidewall profile of the nanosheets can be adjusted to modify the current density at the interface with the source/drain region.
Claims 7, 15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang, as applied to claim 1 above, in view of Choi et al. US 20240096945 A1 (hereinafter referred to as Choi).
Regarding claim 7, Jang teaches the method of claim 1 but fails to teach wherein the first epitaxial region is p-type and the second epitaxial region is p-type.
Nevertheless, Choi teaches an “integrated circuit device 100” comprising “nanosheet stacks NSS” and “source/drain regions 130” formed of two stacked layers (para. 0031,0041). “Source/drain regions 130” may be n-doped or p-doped and the nanosheets in “nanosheet stacks NSS” are oppositely doped (para. 0052). This determines whether the transistors in the “integrated circuit device 100” are p-type or n-type. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “semiconductor device 100” in Jang can alternatively be an P-type device instead of an N-type device by forming the “source/drain regions 150” with p-type dopants.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Jang with the dopants taught in Choi. The conductivity type can be changed to p-type by doping the first and second epitaxial region with p-type dopants, forming a P-type transistor device.
Regarding claim 15, Jang teaches the method of claim 9, wherein the first semiconductor material is silicon (“channel structures 140” comprise silicon, para. 0028), the second semiconductor material is silicon germanium (“first epitaxial layer 152” comprises SiGe doped with phosphorus, para. 0032).
However, Jang fails to teach the third semiconductor material is silicon germanium having a different composition than the second semiconductor material.
Nevertheless, Choi teaches “source/drain regions 130” comprising a “lower main body layer 132” and “upper main body layer 136” both made of SiGe (para. 0041). The “upper main body layer 136” may have a higher Ge concentration than the “lower main body layer 132” (para. 0041). Adjustment of the germanium concentration in the “source/drain regions 130” affects the strain imparted on channels “first, second, and third nanosheets N1, N2, and N3”; higher germanium concentrations apply greater strain to “first, second, and third nanosheets N1, N2, and N3”, increasing carrier mobility (para. 0063). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the germanium concentration of “second epitaxial layer 152” can be increased to impart greater strain on “channel structures 140” to improve carrier mobility.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the third semiconductor material in Jang with the silicon germanium composition taught in Choi. Silicon germanium with a greater concentration of germanium applies greater strain on the nanostructure.
Regarding claim 17, Jang teaches
A method (method of forming “semiconductor device 100” para. 0021 FIG. 2) comprising:
forming a plurality of nanostructures (“channel structures 140” para. 0022) over a semiconductor fin (“active region 105” para. 0022), wherein the nanostructures comprise silicon (“channel structures 140” include silicon, para. 0028);
forming a source/drain region (“source/drain region 150” para. 0022) on the plurality of nanostructures, comprising:
forming a first silicon germanium material on the semiconductor fin and on the plurality of nanostructures (“first epitaxial layers 152” comprise SiGeP, para. 0032); and
forming a second material on the first silicon germanium material (“second epitaxial layer 154” is formed on “first epitaxial layers 152”, para. 0033),
forming a gate structure (“gate structure 160” para. 0022) on the plurality of nanostructures.
However, Jang fails to teach forming a second silicon germanium material on the first silicon germanium material, wherein the second silicon germanium material has a higher concentration of germanium than the first silicon germanium material.
Nevertheless, Choi teaches “source/drain regions 130” comprising a “lower main body layer 132” and “upper main body layer 136” both made of SiGe (para. 0041). The “upper main body layer 136” may have a higher Ge concentration than the “lower main body layer 132” (para. 0041). Adjustment of the germanium concentration in the “source/drain regions 130” affects the strain imparted on channels “first, second, and third nanosheets N1, N2, and N3”; higher germanium concentrations apply greater strain to “first, second, and third nanosheets N1, N2, and N3”, increasing carrier mobility (para. 0063). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the germanium concentration of “second epitaxial layer 152” can be increased to impart greater strain on “channel structures 140” to improve carrier mobility.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the third semiconductor material in Jang with the silicon germanium composition taught in Choi. Silicon germanium with a greater concentration of germanium applies greater strain on the nanostructures.
Regarding claim 18, Jang teaches the method of claim 17, wherein the second silicon germanium material has a higher concentration of dopants than the first silicon germanium material (“concentration of impurities included in the first epitaxial layer 152 may be within a range of approximately 2×10.sup.20/cm.sup.3 to 8×10.sup.20/cm.sup.3” para. 0032, while “concentration of impurities included in the second epitaxial layer 154 may be within a range of approximately 3.1×10.sup.21/cm.sup.3to 3.9×10.sup.21/cm.sup.3”, Jang para. 0034).
Regarding claim 19, Jang teaches the method of claim 18, wherein the dopants are p-type dopants.
Nevertheless, Choi teaches an “integrated circuit device 100” comprising “nanosheet stacks NSS” and “source/drain regions 130” formed of two stacked layers (para. 0031,0041). “Source/drain regions 130” may be n-doped or p-doped and the nanosheets in “nanosheet stacks NSS” are oppositely doped (para. 0052). This determines whether the transistors in the “integrated circuit device 100” are p-type or n-type. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “semiconductor device 100” in Jang can alternatively be an P-type device instead of an N-type device by forming the “source/drain regions 150” with p-type dopants.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Jang with the dopants taught in Choi. The conductivity type can be changed to p-type by doping the first and second epitaxial region with p-type dopants, forming a P-type transistor device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 17 above, in view of Cho et al. US 20200381546 A1 (hereinafter referred to as Cho).
Jang teaches the method of claim 17 but fails to teach wherein the plurality of nanostructures protrudes into a sidewall of the source/drain region.
Nevertheless, Cho teaches
wherein the plurality of nanostructures protrudes into a sidewall of the source/drain region (“the sidewalls of the semiconductor pattern 132a may protrude in the first direction from the outer wall of the first spacer 144a” and into “first semiconductor layer 150”, para. 0025, 0045 FIG. 4A).
Jang and Cho teach finfets with nanostructure channels. The sidewalls of “semiconductor pattern 132a” protrude into “first semiconductor layer 150” unlike the “channel layers 141-143” in Jang that are substantially coplanar with the “internal spacer layers 130” (Jang para. 0030). By protruding into the source/drain region, the interface between “semiconductor patterns 132” and “first semiconductor layer 150” is increased. The examiner understands that with this increased surface area, the current density passing at the interface may be reduced for a same total current passing through “channel layers 141-143” as taught in Jang. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having “channel structures 140” protruding into “source/drain region 150” can adjust the current density at the interface between “channel structures 140”, “first layer 152A”, and “second epitaxial layer 154”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Jang with the nanostructures and spacers as taught in Cho. The current path between the source/drain region and the nanostructures can be adjusted by forming them such that the nanostructures protrude into the source/drain region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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