DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki et al. (US20120043589A1) in view of Kamino et al. (US20180358394A1).
Regarding claim 1, Nozaki teaches in Fig. 3B a pixel sensor, comprising:
a substrate (330, 340, 370, and/or 380) {[0025, 0026]};
a photodiode region (310) in the substrate (330, 340, 370, and/or 380) {[0025]};
a floating diffusion region (320) in the substrate (330, 340, 370, and/or 380) {[0026]};
a transfer gate contact (360) in the substrate (330, 340, 370, and/or 380) between the photodiode region (310) and the floating diffusion region (320) {[0026]}.
Nozaki does not teach a plurality of silicon-fluorine bonds located at an interface between the transfer gate contact and the substrate.
In an analogous art, Kamino teaches in Fig. 19 and paragraph [0083, 0094] a plurality of silicon-fluorine bonds located at an interface between a transfer gate contact (GE) and a substrate (channel region). More specifically, Kamino teaches creating silicon-fluorine bonds in an interface between a gate insulating film and a silicon channel region of a substrate, where the gate insulating film is disposed between the transfer gate contact and the channel region of the substrate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor based on the teachings of Kamino – such that a plurality of silicon-fluorine bonds are located at an interface between the transfer gate contact and the substrate – so: (1) the dangling bond existing in the transfer transistor can be reduced, (2) the interface level of the transfer transistor can be reduced, and (3) the “dark current” of the image sensor can be reduced. Kamino [0083].
Regarding claim 2, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, and Nozaki further teaches wherein an angle between a bottom surface of the transfer gate contact (360) and a sidewall of the transfer gate contact (360) is in a range of approximately 70 degrees to approximately 90 degrees.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 7, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, and Nozaki further teaches further comprising: an oxide layer (350) between the interface (modified interface between gate oxide layer 350 and substrate 330, 340, 370, and/or 380) and the transfer gate contact (360) {[0026]}.
Moreover, Kamino teaches in paragraph [0049] the gate insulating film (sandwiching the silicon-fluorine bonds in the interface with the substrate) is silicon oxide. And the motivation for Kamino’s modification of Nozaki’s pixel sensor is identified with respect to base claim 1.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Kamino as applied to claim 1 above, and further in view of Takahashi (US20220254823A1).
Regarding claim 3, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, but Nozaki does not teach wherein a ratio between a depth of the transfer gate contact to a width of the transfer gate contact is in a range of approximately 3 to approximately 6.
In an analogous art pertaining to an imaging device having a sensor pixel (2), a photodiode (PD), a floating diffusion (FD) and a transfer transistor (TR) {see e.g., Fig. 3}, Takahashi teaches in Fig. 8 a ratio between a depth of the transfer gate contact to a width of the transfer gate contact is in a range of approximately 3 to approximately 6 {[0109], It is preferable that the transfer gate electrode TG be formed to have a cross-sectional shape in which b+c<6d and d>e are satisfied (where 0<b<3.5d and 0<c<3.5d are satisfied); e.g., where b+c is the depth and d is the width (i.e., depth/width < 6)}. Takahashi teaches the aspect ratio is a result-effective parameter for improving etching and the introduction of the conduction-type impurities {[0109]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Kamino based on the teachings of Takahashi, as identified above, for the purpose of identifying an optimal or workable ratio of depth to width through routine experimentation that would make it easier to form the transfer gate electrode TG and the first conduction-type region 130 in the desired region. Takahashi [0109].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Kamino as applied to claim 1 above, and further in view of Birner et al. (US20060017132A1).
Regarding claim 4, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, and Nozaki further teaches further comprising:
a shallow trench isolation (STI) structure (STI) adjacent to the floating diffusion region (320) {[0032]}.
Nozaki does not teach another plurality of silicon-fluorine bonds located at an interface between the STI structure and the substrate.
In an analogous art, Birner teaches in Fig. 2D performing a second surface treatment operation to form a plurality of silicon-fluorine bonds at an interface between an STI structure and a substrate (2) {[0053, 0059]; fluorine-containing particles 12 are implanted into the semiconductor arrangement 1 by means of shallow trench implantations}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Kamino based on the teachings of Birner – such that another plurality of silicon-fluorine bonds are located at an interface between the STI structure and the substrate – for the purpose of improving the saturation and the electrical properties of the interface of the silicon semiconductor body into which the fluorine particle are introduced. Birner [0021].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Kamino as applied to claim 1 above, and further in view of Satou (US20060099748A1).
Regarding claim 5, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, but Nozaki does not teach wherein a ratio of a concentration of fluorine located at the interface to a concentration of boron located at the interface is based on a threshold voltage associated with the transfer gate contact and a saturation current associated with the floating diffusion region.
In an analogous art pertaining to a similar problem, faced by the instant inventors, of obtaining each of a workable threshold voltage and a saturation current based on a ratio of fluorine to boron implanted within a transistor device {see e.g., [0075] of the instant application}, Satou teaches a ratio of a concentration of fluorine located at an interface to a concentration of boron located at the interface is based on a threshold voltage associated with a transfer gate contact and a saturation current associated with a floating diffusion region. More specifically, Satou teaches that a ratio of fluorine to boron is a result-effective parameter for regulating a threshold voltage and saturation current in an FET device {Fig. 6; [0053, 0088]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Kamino based on the teachings of Satou, as identified above, for the purpose of acquiring each of a threshold voltage and a saturation current within an optimal or workable range through routine experimentation in which a concentration ratio of fluorine to boron is varied. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Kamino as applied to claim 1 above, and further in view of Berger et al. (US20210305306A1).
Regarding claim 6, Nozaki as modified by Kamino teaches the pixel sensor of claim 1, but Nozaki does not teach wherein a size of the pixel sensor is in a range of approximately 0.1 micrometers (μm) to 1.0 μm.
In an analogous art, Berger teaches in Fig. 3 a size of the pixel sensor (1) is in a range of approximately 0.1 micrometers (um) to 1.0 um {[0079], the opening 300 of each pixel of the sensor has lateral dimensions less than or equal to 1 μm}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Kamino based on the teachings of Berger, as identified above, for the purpose of decreasing the semiconductor area required for each pixel sensor or increasing the density of the pixel sensors per unit area.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Kamino as applied to claim 7 above, and further in view of Ishino et al. (US20160343761A1).
Regarding claim 8, Nozaki as modified by Kamino teaches the pixel sensor of claim 7, but Nozaki does not teach wherein a thickness of the oxide layer is in a range of approximately 1 Ångström to approximately 96 Ångströms.
In an analogous art pertaining to an imaging device having a photodiode (PD), a floating diffusion (104) and a transfer transistor (TX) {see e.g., Figs. 1B and 2}, Ishino teaches a thickness of the oxide layer is in a range of approximately 1 Angstrom to approximately 96 Angstroms {[0033], oxide thickness (EOT) of approximately 80 angstroms, … oxide thickness (EOT) of 35 angstroms or less}. Ishino further teaches the thickness of an oxide layer for a gate insulating film is a result-effective parameter for varying the driving voltage of a transfer gate transistor {[0033]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Kamino based on the teachings of Ishino, as identified above, for the purpose of identifying an optimal or workable driving voltage through routine experimentation. Ishino [0033].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Birner.
Regarding claim 9, Nozaki teaches in Fig. 4 a semiconductor structure, comprising:
a (440, 470, and/or 480) including a trench (435) {[0033]};
an oxide layer (450) that lines the trench (435) and contacts a photodiode region (410) and a floating diffusion region (420) {[0033]}; and
a polysilicon layer (463 and/or 464) filling the trench (435) {[0034]}.
Nozaki does not teach a bottom surface of the trench and sidewalls of the trench include a plurality of silicon-fluorine bonds.
Birner teaches a bottom surface of the trench and sidewalls of the trench (8) include a plurality of silicon-fluorine bonds {Fig. 2D; [0022; 0059; 0039], the fluorine-containing particles are introduced into the … silicon semiconductor body}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s semiconductor structure based on the teachings of Birner, as identified above, for the purpose of improving the saturation and the electrical properties of the interface of the silicon semiconductor body into which the fluorine particle are introduced. Birner [0021].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Birner as applied to claim 9 above, and further in view of Zhao (CN107919387A).
Regarding claim 10, Nozaki as modified by Birner teaches the semiconductor structure of claim 9, but Nozaki does not teach wherein a fluorine concentration associated with the trench is in a range of approximately 1011 ions per square centimeter (cm2) to approximately 1013 ions per cm2.
In an analogous art pertaining to a problem of selecting a concentration of fluorine ions to achieve a desired threshold voltage {see, e.g., [0075] of the instant application}, Zhao teaches wherein a fluorine concentration associated with the trench is in a range of approximately 1011 ions per square centimeter (cm2) to approximately 1013 ions per cm2 {Page 2, first paragraph, the pre-ion implanted injection source includes one or more of carbon ions, fluoride ions; Page 2, second paragraph, pre-ion implantation is 1×1013 - 1×1014 ions/cm2}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s semiconductor structure as modified by Birner based on the teachings of Zhao, as identified above, for the purpose of stabilizing the threshold voltage. Zhao page 2, seventh paragraph, and page 3, first paragraph.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Birner as applied to claim 9 above, and further in view of Huang et al. (US20200411585A1).
Regarding claim 11, Nozaki as modified by Birner teaches the semiconductor structure of claim 9, but Nozaki does not teach wherein the bottom surface and the sidewalls of the trench are implanted with boron atoms.
In an analogous art, Huang teaches that a bottom surface and sidewalls of the trench are implanted with boron atoms {[0002], Typically, boron is implanted at the sidewalls of the trench to ensure such passivation}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s semiconductor structure as modified by Birner based on the teachings of Huang, as identified above, for the purpose ensur[ing] … passivation. Huang [0002].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Birner as applied to claim 9 above, and further in view of Shin et al. (KR20080008851A).
Regarding claim 12, Nozaki as modified by Birner teaches the semiconductor structure of claim 9, but Nozaki does not teach wherein the silicon-fluorine bonds are located within a range of approximately 0 nanometers (nm) to approximately 500 nm beneath a surface of the trench.
Shin teaches the silicon-fluorine bonds are located within a range of approximately 0 nanometers (nm) to approximately 500 nm beneath a surface {[0046], by injecting fluorine (F) ions to form the third channel region 116, the fluorine (F) ions are combined with the silicon lattice of the semiconductor substrate 100}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s semiconductor structure as modified by Birner based on the teachings of Shin, as identified above, for the purpose of preventing boron from diffusing outside of channel region 114 and thereby lowering an efficiency of charge transfer {[0045-0046]}. Because Shin’s fluorine ions are combined with the silicon lattice of the semiconductor substrate, it follows the silicon-fluorine bonds exist at and immediately below the surface of the semiconductor substrate.
Moreover, Birner teaches in Fig. 2D and paragraph [0029] it is possible to ensure more or less precisely that the fluorine-containing particles are arranged as near as possible to the interface between semiconductor body and dielectric layer after the implantation. As a result of the thermal step following the implantation, the fluorine-containing particles or the fluorine ions can additionally be added very near to the interface or directly to the interface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s semiconductor structure as modified by Birner above based on the teachings of Shin, as identified above, for the purpose whereby the saturation effect according to the invention is even greater. Birner [0029].
Claim(s) 13, 15-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Huang and Kamino.
Regarding claim 13, Nozaki teaches in Fig. 3B a pixel sensor, comprising:
a photodiode region (310) in a substrate (330, 340, 370, and/or 380) {[0025]};
a floating diffusion region (320) in the substrate (330, 340, 370, and/or 380) {[0026]};
a transfer gate contact (360) in the substrate (330, 340, 370, and/or 380) between the photodiode region (310) and the floating diffusion region (320) {[0026]}.
Nozaki does not teach a drain extension region in the substrate between the floating diffusion region and the transfer gate contact.
In an analogous art, Huang teaches in Fig. 11 and paragraph [0033] a drain extension region (630) in a substrate (110) between a floating diffusion region (810) and a transfer gate contact (240). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor based on the teachings of Huang – such that a drain extension region is disposed in the substrate between the floating diffusion region and the transfer gate contact – to prevent blooming that otherwise may result when such excess photo-induced electrons diffuse to neighboring pixels. Huang [0033].
Nozaki does not teach a plurality of silicon-fluorine bonds located at an interface between the transfer gate contact and the substrate.
Kamino teaches in Fig. 19 and paragraph [0083, 0094] a plurality of silicon-fluorine bonds located at an interface between a transfer gate contact (GE) and a substrate (channel region). More specifically, Kamino teaches creating silicon-fluorine bonds in an interface between a gate insulating film and a silicon channel region of a substrate, where the gate insulating film is disposed between the transfer gate contact and the channel region of the substrate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Huang based on the teachings of Kamino – such that a plurality of silicon-fluorine bonds are located at an interface between the transfer gate contact and the substrate – so: (1) the dangling bond existing in the transfer transistor can be reduced, (2) the interface level of the transfer transistor can be reduced, and (3) the “dark current” of the image sensor can be reduced. Kamino [0083].
Regarding claim 15, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, and Nozaki further teaches further comprising:
a doped region (385) in the substrate (330, 340, 370, and/or 380) under the transfer gate contact (360) {[0027]}.
Nozaki does not teach the plurality of silicon-fluorine bonds located at an interface between the transfer gate contact and the doped region. However, a consequence of Kamino’s modification identified with respect to base claim 13 is that the plurality of silicon-fluorine bonds would be located at an interface between Kamino’s transfer gate contact (360) and doped region (385). The motivation for this modification is identified with respect to base claim 13.
Regarding claim 16, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, and Nozaki further teaches wherein a depth of the transfer gate contact (360) in the substrate is greater than a width of the transfer gate contact (360).
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 17, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, but Nozaki does not teach wherein the transfer gate contact is located laterally between the drain extension region and the photodiode region.
Huang teaches in Fig. 11 and paragraph [0033] a transfer gate contact (240) is located laterally between a drain extension region (630) and a photodiode region (region of 230, 630, and 820). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Huang and Kamino based on the further teachings of Huang – such that the transfer gate contact is located laterally between the drain extension region and the photodiode region – to prevent blooming that otherwise may result when such excess photo-induced electrons diffuse to neighboring pixels. Huang [0033].
Regarding claim 18, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, and Nozaki further teaches wherein an angle between a bottom surface of the transfer gate contact (360) and a sidewall of the transfer gate contact (360) is in a range of approximately 70 degrees to approximately 90 degrees.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 20, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, and Nozaki further teaches further comprising: an oxide layer (350) between the interface (modified interface between gate oxide layer 350 and substrate 330, 340, 370, and/or 380) and the transfer gate contact (360) {[0026]}.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Huang and Kamino as applied to claim 13 above, and further in view of Birner.
Regarding claim 14, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, but Nozaki does not teach wherein the plurality of silicon-fluorine bonds is located at an interface between the transfer gate contact and the drain extension region.
Birner teaches a bottom surface of a trench (8) and sidewalls of the trench (8) include a plurality of silicon-fluorine bonds {Fig. 2D; [0022; 0059; 0039], the fluorine-containing particles are introduced into the … silicon semiconductor body}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Huang and Kamino based on the teachings of Birner, as identified above, for the purpose of improving the saturation and the electrical properties of the interface of the silicon semiconductor body into which the fluorine particle are introduced. Birner [0021]. A consequence of this modification is that the plurality of silicon-fluorine bonds would be located at an interface between the transfer gate contact and the drain extension region.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki in view of Huang and Kamino as applied to claim 13 above, and further in view of Satou.
Regarding claim 19, Nozaki as modified by Huang and Kamino teaches the pixel sensor of claim 13, but Nozaki does not teach wherein a ratio of a concentration of fluorine located at the interface, to a concentration of boron located at the interface, is based on a threshold voltage associated with the transfer gate contact and a saturation current associated with the floating diffusion region.
Satou teaches a ratio of a concentration of fluorine located at an interface to a concentration of boron located at the interface is based on a threshold voltage associated with a transfer gate contact and a saturation current associated with a floating diffusion region. More specifically, Satou teaches that a ratio of fluorine to boron is a result-effective parameter for regulating a threshold voltage and saturation current in an FET device {Fig. 6; [0053, 0088]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nozaki’s pixel sensor as modified by Huang and Kamino based on the teachings of Satou, as identified above, for the purpose of acquiring each of a threshold voltage and a saturation current within an optimal or workable range through routine experimentation in which a concentration ratio of fluorine to boron is varied. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oh et al. (US20170040364A1) teaches image sensors may include a semiconductor substrate including a plurality of pixel areas, a photodiode provided in the semiconductor substrate in one of the plurality of pixel areas and a transfer transistor having a transfer gate electrode. A portion of the transfer gate electrode may be in the semiconductor substrate and may extend toward the photodiode. The image sensors may also include a floating diffusion configured to accumulate charges transferred from the photodiode by the transfer transistor, and the floating diffusion may include a first area and a second area disposed on different sides of the transfer gate electrode.
Conclusion
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/D.W.W./ Examiner, Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891
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