DETAILED ACTION
This Office action is in response to the filing of this application on 29 July 2024. Claims 1-20 are pending in the application.
This application is a continuation of application Serial No. 18/329,396, filed on 05 June 2023, which is a continuation of application Serial No. 16/926,528, filed on 10 July 2020, now US Patent 11,670,551.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo et al., US 2016/0380056, in view of Wu et al., US 2013/0168771.
With respect to claim 9, Yeo et al. disclose a method comprising:
providing a workpiece including a first fin-shaped structure 22 and a second fin-shaped structure 22, as shown in Fig. 12B;
forming a semiconductor cap layer 28 over the first fin-shaped structure 22 and the second fin-shaped structure 22, as shown in Fig. 12B and 2, see paragraphs [0026]; and
performing a source/drain activation anneal, see paragraph [0031]. It would have
been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the amorphous semiconductor cap layer 28 would have been crystallized during the source/drain activation anneal.
Although Yeo et al. disclose providing a workpiece including a first fin-shaped structure 22 and a second fin-shaped structure 22, Yeo et al. lack anticipation of the first fin-shaped structure includes a first top portion, a middle portion, and a first bottom portion, wherein the second fin-shaped structure includes a second top potion and a second bottom portion, and wherein the second top portion and the middle portion include a same composition that is different from a composition of the first top portion. In the same field of endeavor, Wu et al. disclose a method for fabricating an integrated circuit device that includes a complementary metal-oxide-semiconductor (CMOS) fin-like field effect transistor (FinFET) device comprising: providing a workpiece, shown in Fig. 31, including a first fin-shaped structure 212a/222/822 and a second fin-shaped structure 212c/226/824, wherein the first fin-shaped structure 212a/222/822 includes a first top portion 822, a middle portion 222, and a first bottom portion 212a, wherein the second fin-shaped structure 212c/226/824 includes a second top portion 824 and a second bottom portion 212c, and wherein the second top portion 824 and the middle portion 222 include a same composition (III-V material) that is different from a composition of the first top portion 822 (germanium), see paragraph [0061]. Wu et al. disclose that the depositing separate materials for the NMOS FinFET and the PMOS FinFET devices of the CMOS FinFET improves the intrinsic carrier mobility in the channel region, see paragraph [0064]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the channel materials of Wu et al. in fabricating a CMOS FinFET in the known method of Yeo et al., thereby fabricating a CMOS FinFET with improved carrier mobility.
With respect to claim 10, Yeo et al. disclose forming the semiconductor cap layer 28 includes depositing the semiconductor cap layer 28 using atomic layer deposition (ALD), see paragraph [0026].
With respect to claim 11, Yeo et al. disclose forming the semiconductor cap layer includes epitaxially growing the semiconductor cap layer, [0025].
With respect to claim 13, the combination of Yeo et al. and Wu et al. would result in forming the semiconductor cap layer 28 on the first top portion, the middle portion, and the second top portion of the fin-shaped structures, since Yeo et al. show in Fig. 12B that the cap layer 28 is formed on all exposes surfaces of the fin-shaped structures.
Claims 12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo et al., US 2016/0380056, in view of Wu et al., US 2013/0168771, as applied to claim 9 above, and further in view of Wang et al., US 2019/0157154.
Yeo et al. and Wu et al. are applied as above. With respect to claim 12, in the method of Yeo et al., crystalizing the semiconductor cap layer 28 is at a first temperature (the temperature of the source/drain activation anneal); and wherein the method further comprises: forming a gate structure 34 over the first fin-shaped structure 22 and the second fin-shaped structure 22, and after the forming of the gate structure 34, see Figs. 3A and 3B, and performing an anneal at a second temperature (400° C. and about 1,100° C), see paragraph [0046]. However, Yeo et al. fail to teach performing an anneal at a second temperature lower than the first temperature, since Yeo et al. do not disclose the temperature at which the source/drain activation anneal is performed. In the same field of endeavor, Wang et al. disclose in paragraph [0030] that an activation anneal can be performed at a temperature of about 950° C. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the activation anneal in the known method of Yeo et al could have been performed at a temperature of about 950° C, and the second temperature (400° C. and about 1,100° C) would be lower than the first temperature.
With respect to claim 14, although Yeo et al. disclose an isolation structure 24 between fins 22, as shown in Fig. 3B, Yeo fails to teach a liner layer disposed on sidewalls of the first bottom portion and the second bottom portion, and an isolation feature disposed over the liner layer and between the first bottom portion and the second bottom portion; and wherein the semiconductor cap layer is disposed above the liner layer. In the same field of endeavor, Wang discloses an isolation structure which includes a liner layer 1220 disposed on sidewalls of the first bottom portion and the second bottom portion of first and second fin-shaped structures, and an isolation feature 1300 disposed over the liner layer 1220, as shown in Figs. 13 and 14. and between the first bottom portion and the second bottom portion; and wherein the semiconductor cap layer is disposed above the liner layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the isolation structure of Wang et al. could have been formed in the known method of Yeo et al., since both isolation structures are functionally equivalent. Formation of the isolation structure of Wang et al in the known method of Yeo et al would result in the semiconductor cap layer 28 being disposed above the liner layer.
With respect to claim 15, Wang et al. disclose that the first bottom portion 320 of fin 1200 and the second bottom portion 400 of fin 1210 are of different conductivity types, see paragraphs [0028]-[0030]. Since the combination of Yeo et al. and Wu et al. fabricate a CMOS FinFET, in light of the disclosure of Wang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first bottom portion 212a and the second bottom portion 212c could be of different conductivity types.
Claims 16, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo et al., US 2016/0380056, in view of Wang et al., US 2019/0157154.
Yeo et al. disclose a method comprising:
providing a workpiece including a first fin-shaped structure 22 and a second fin-shaped structure, as shown in Fig. 12B;
forming a semiconductor cap layer 28 over the first fin-shaped structure 22 and the second fin-shaped structure 22;
performing a first anneal at a first temperature, see paragraph [0031];
forming a gate structure 34 over channel regions of the first fin-shaped structure 22 and the second fin-shaped structure 22, see Fig. 12B; and
after the forming of the gate structure, performing a second anneal at a second temperature, see paragraph [0046].
However, Yeo et al. fail to teach performing an anneal at a second temperature lower than the first temperature, since Yeo et al. do not disclose the temperature at which the source/drain activation anneal is performed. In the same field of endeavor, Wang et al. disclose in paragraph [0030] that an activation anneal can be performed at a temperature of about 950° C. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the activation anneal in the known method of Yeo et al could have been performed at a temperature of about 950° C, and the second temperature (400° C. and about 1,100° C) would be lower than the first temperature.
With respect to claim 18, Wang et al. disclose a first fin-shaped structure 1200 includes silicon and germanium 900 and the second fin-shaped structure 1210 includes silicon 410, as shown in Fig. 12. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first fin-shaped structure 22 could include silicon and germanium and the second fin-shaped structure 22 could comprise silicon in the known method of Yeo et al., in order to fabricate a CMOS FinFET having improved carrier mobility and reduced channel resistance.
With respect to claim 19, Yeo et al. disclose forming the semiconductor cap layer 28 includes depositing the semiconductor cap layer using atomic layer deposition (ALD), see paragraph [0026].
With respect to claim 20, Yeo et al. disclose that forming the semiconductor cap layer includes epitaxially growing the semiconductor cap layer, see paragraph [0025].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 9 of U.S. Patent No. 11,670,551 in view of Yeo et al., US 2016/0380056. Both the patented claims and the pending claims recite a method comprising providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate; depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure; forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure; epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner; and crystalizing/annealing the cap layer. However, the pending claims further require forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure. However, it would have been obvious to the skilled artisan to form forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure, as shown in Figs. 5A and 5B of Yeo et al.
Claims 9-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 7, and 9 of U.S. Patent No. 11,670,551 in view of Wu et al., US 2013/0168771. Both the patented claims and the pending claims recite a method comprising forming a first fin-shaped structure and a second fin-shaped structure of different semiconductor materials, forming a silicon cap layer over the fin-shaped structures, and crystallizing/annealing the silicon cap layer. Admittedly, the patented claims do not require the first fin-shaped structure to include a first top portion, a middle portion, and a first bottom portion, wherein the second fin-shaped structure includes a second top potion and a second bottom portion, and wherein the second top portion and the middle portion include a same composition that is different from a composition of the first top portion. However, Wu et al. disclose a method for fabricating an integrated circuit device that includes a complementary metal-oxide-semiconductor (CMOS) fin-like field effect transistor (FinFET) device comprising: providing a workpiece, shown in Fig. 31, including a first fin-shaped structure 212a/222/822 and a second fin-shaped structure 212c/226/824, wherein the first fin-shaped structure 212a/222/822 includes a first top portion 822, a middle portion 222, and a first bottom portion 212a, wherein the second fin-shaped structure 212c/226/824 includes a second top portion 824 and a second bottom portion 212c, and wherein the second top portion 824 and the middle portion 222 include a same composition (III-V material) that is different from a composition of the first top portion 822 (germanium), see paragraph [0061]. Wu et al. disclose that the depositing separate materials for the NMOS FinFET and the PMOS FinFET devices of the CMOS FinFET improves the intrinsic carrier mobility in the channel region, see paragraph [0064]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the fins disclosed by Wu et al. could have been used in the method of the patented claims to fabricate a CMOS FinFET with improved carrier mobility.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-13 of U.S. Patent No. 11,670,551. Although the claims at issue are not identical, they are not patentably distinct from each other because both the patented claims and the pending claims recite a method which includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure; forming a semiconductor cap layer over the first fin-shaped structure and the second fin-shaped structure; performing a first anneal at a first temperature; forming a gate structure over channel regions of the first fin-shaped structure and the second fin-shaped structure; and after the forming of the gate structure, performing a second anneal at a second temperature lower than the first temperature, wherein performing the first anneal is at a first pressure, and wherein performing the second anneal is at a second pressure greater than the first pressure
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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