DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,062,579. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-20 is similar to that of the claimed limitations of U.S. Patent No. 12,062,579 as claimed in claims 1-16. Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A method of processing a substrate comprising: selectively depositing a seed layer over an n-channel metal-oxide semiconductor (NMOS) source/drain region of a NMOS device and a p-channel metal-oxide semiconductors (PMOS) source/drain region of a PMOS device, the seed layer comprising both silicon and germanium; and depositing, a metal silicide over the NMOS source/drain region and the PMOS source/drain region after depositing the seed layer.
2. The method of claim 1, wherein the seed layer is a SiGe layer with a molecular germanium concentration of about 5% to about 75% of the seed layer.
3. The method of claim 2, wherein the seed layer is deposited by a silicon and germanium containing precursor.
4. The method of claim 1, wherein the seed layer has a thickness of less than 5 nm.
5. The method of claim 1, wherein the seed layer is deposited during a thermal deposition process in an epitaxial chamber.
6. The method of claim 1, wherein the seed layer is consumed during the depositing of the metal silicide.
7. The method of claim 6, wherein the metal silicide comprises silicon, germanium, and at least one of titanium, nickel, cobalt, or platinum.
8. The method of claim 1, wherein a contact metal layer is deposited after the deposition of the metal silicide and on the metal silicide.
9. A method of processing a substrate comprising: depositing a first seed layer over an n-channel metal-oxide semiconductor (NMOS) source/drain region of a NMOS device within a first processing chamber, the first seed layer comprising silicon, germanium, and one or more dopants; depositing a second seed layer over an a p-channel metal-oxide semiconductors (PMOS) source/drain region of a PMOS device within the first processing chamber, the second seed layer comprising silicon, germanium, and one or more dopants; depositing, in a second processing chamber, a metal silicide over the NMOS source/drain and the PMOS source region after depositing the first seed layer and second seed layer, the first seed layer and second seed layer being consumed during the deposition of the metal silicide.
10. The method of claim 9, wherein depositing the metal silicide forms a metal silicide layer with a thickness of about double a thickness of the first seed layer and second seed layer before the first seed layer and second seed layer were consumed. 11. The method of claim 9, wherein the one or more dopants of the first seed layer are different than the one or more dopants of the second seed layer. 12. The method of claim 11, wherein the one or more dopants comprise, phosphorus, boron, carbon, gallium, arsenic, or tin. 13. The method of claim 12, wherein depositing, in a second processing chamber, a metal silicide comprises a thermal only chemical vapor deposition process. 14. The method of claim 9, further comprising forming one or more gate structures on a substrate, the one or more gate structures disposed between the PMOS source/drain region of the PMOS device and the NMOS source/drain region of the NMOS device. 15. The method of claim 14, wherein the first seed layer and second seed layer are deposited at a temperature of less than 500 °C and the one or more gate structures are formed before depositing the first seed layer and second seed layer. 16. The method of claim 14, wherein the first seed layer and second seed layer are deposited at a temperature of about 500 °C to about 750 °C and the one or more gate structures are formed after the deposition of the seed layer and before the deposition of the metal silicide. 17. A method of processing a substrate comprising: positioning a substrate into a processing chamber, the substrate comprising: a n-channel metal-oxide semiconductor (NMOS) device; and a p-channel metal-oxide semiconductors (PMOS) device; selectively depositing, with an epitaxial process in the processing chamber, a seed layer over an NMOS source/drain region of the NMOS device and over a PMOS source/drain region of the PMOS device, the seed layer comprising both silicon and germanium; forming, in the processing chamber and after depositing the seed layer, a metal silicide simultaneously over the NMOS source/drain and the PMOS source region, the seed layer being consumed during the forming of the metal silicide, the metal silicide comprising silicon and germanium and at least one of titanium, nickel, cobalt, or platinum. 18. The method of claim 17, wherein the seed layer is an un-doped silicon and germanium layer. 19. The method of claim 17, wherein forming metal silicide is a thermal process. 20. The method of claim 17, wherein forming metal silicide is a selective reaction process, the selective reaction process reacting only with the seed layer to form the metal silicide.
U.S. Patent No. 12,062,579:
1. A method of processing a substrate comprising: positioning a substrate having an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductors (PMOS) device disposed thereon into a first processing chamber; selectively depositing a first seed layer over an NMOS source/drain region of the NMOS device and a PMOS source/drain region of the PMOS device, the first seed layer comprising both silicon and germanium; depositing, in a second processing chamber, a second seed layer over a PMOS source/drain region of the PMOS device, the second seed layer comprising silicon; and forming, through chemical vapor deposition, a metal silicide simultaneously over the NMOS source/drain region and the PMOS source/drain region after depositing the first and second seed layers.
2. The method of claim 1, wherein the first seed layer is a SiGe layer with a molecular germanium concentration of about 5% to about 75% of the first seed layer.
3. The method of claim 2, wherein the first seed layer is deposited by a silicon and germanium containing precursor.
4. The method of claim 1, wherein the first seed layer has a thickness of less than 5 nm.
5. The method of claim 1, wherein the first seed layer is deposited during a thermal deposition process.
6. The method of claim 1, wherein the first seed layer is consumed during the depositing of the metal silicide.
7. The method of claim 6, wherein the metal silicide comprises silicon, germanium, and at least one of titanium, nickel, cobalt, or platinum.
8. The method of claim 1, wherein a contact metal layer is deposited after the deposition of the metal silicide and on the metal silicide.
9. A method of processing a substrate comprising: positioning a substrate having an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductors (PMOS) device disposed thereon into a first processing chamber; selectively depositing a first seed layer over an NMOS source/drain region of the NMOS device within the first processing chamber, the first seed layer comprising both silicon and germanium; selectively depositing, within a second processing chamber, a second seed layer over a PMOS source/drain region of the PMOS device, the second seed layer comprising both silicon and germanium; and depositing a metal silicide simultaneously over the NMOS source/drain and the PMOS source region after depositing the first seed layer and the second seed layer, the first seed layer and the second seed layer being consumed during the deposition of the metal silicide.
10. The method of claim 9, wherein both of the first seed layer and the second seed layer comprise silicon, germanium, and one or more dopants. 11. The method of claim 10, wherein the one or more dopants comprise boron, phosphorous, carbon, gallium, arsenic, or tin. 12. The method of claim 11, wherein the first seed layer further comprises phosphorous and the second seed layer further comprises boron. 13. The method of claim 9, further comprising forming one or more gate structures on the substrate. 14. The method of claim 13, wherein the first seed layer is deposited at a temperature of less than 500° C. and the one or more gate structures are formed before the deposition of the first seed layer. 15. The method of claim 13, wherein the first seed layer is deposited at a temperature of about 500° C. to about 750° C. and the one or more gate structures are formed after the deposition of the first seed layer and before the deposition of the metal silicide. 16. A system for substrate processing comprising: a first process chamber; a robot; a second process chamber; and a controller, the controller configured to perform a method comprising: positioning, by the robot, a substrate having an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductors (PMOS) device disposed thereon onto the first substrate support in the first process chamber; selectively depositing a first seed layer over an NMOS source/drain region of the NMOS device within the first process chamber, the first seed layer comprising both silicon and germanium; selectively depositing, within the second processing chamber, a second seed layer over a PMOS source/drain region of the PMOS device, the second seed layer comprising both silicon and germanium; and depositing a metal silicide simultaneously over the NMOS source/drain and the PMOS source region after depositing the first seed layer and the second seed layer, the first seed layer and the second seed layer being consumed during the deposition of the metal
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticpated by Chidambaram et al. (US 2005/0139872).
Re Claim 1, Chidambaram et al. disclose a method of processing a substrate comprising: selectively depositing a seed layer (224) over an n-channel metal-oxide semiconductor (NMOS) source/drain region of a NMOS device and a p-channel metal-oxide semiconductors (PMOS) source/drain region of a PMOS device (see Fig. 2E, Paragraph [0034]), the seed layer (224) comprising both silicon and germanium (see Fig. 1); and depositing, a metal silicide over the NMOS source/drain region and the PMOS source/drain region after depositing the seed layer (see Figs. 1-2k and related text in Paragraphs [0030])-[0040]).
Re Claim 5, as applied to claim 1 above, Chidambaram et al. disclose all the claimed limitations including wherein the seed layer is deposited during a thermal deposition process (i.e., LPCVD, see Page 2, Paragraph [0025]).
Re Claim 6, as applied to claim 1 above, Chidambaram et al. disclose all the claimed limitations including wherein the seed layer is consumed during the depositing of the metal silicide (see Figs. 1-2k and related text in Paragraphs [0030]-[0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 7 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram et al. (US 2005/0139872) in view of Liang et al. (US 2008/0102573).
Re Claim 2, as applied to claim 1 above, Chidambaram et al. disclose all the claimed limitations including wherein the seed layer is a SiGe layer with predetermined molecular germanium concentration.
However, Chidambaram et al. do not disclose specifically the germanium content being
about 5% to about 75% of the SiGe layer.
Liang et al. disclose the SiGe layer 248 having germanium atomic percentage between 10 % to 50 %, i.e., within the overlapped range of claimed 5% to about 75% (see Paragraph [0026]). Furthermore, the desired Germanium content in the SiGe can be adjusted to desire level by adjusting partial-pressures of Si precursors and Ge precursors (see Paragraph [0025]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Chidambaram et al. reference with germanium content being about 5% to about 75% of the SiGe layer as taught by Liang et al. in order to maintain desired Ge continent in SiGe by optimizing partial-pressures of Si precursors and Ge precursors.
Re Claim 3, as applied to claim 2 above, Chidambaram et al. and Liang et al. in combination disclose all the claimed limitations including wherein the seed layer is deposited by a silicon and germanium containing precursor (see Chidambaram et al. Paragraph [0034] and Liang et al. Paragraph [0025]).
Re Claim 4, as applied to claim 1 above, Chidambaram et al. and Liang et al. in combination disclose all the claimed limitations including wherein the seed layer has a predetermined thickness. Furthermore, the thickness rage at least 5 nm or 50 angstroms disclose in Liang et al. and the thickness outside Chidambaram et al. and Liang et al. disclose can be routinely optimized. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re Claim 7, as applied to claim 6 above, Chidambaram et al. the metal silicide comprises silicon, germanium, and at least one metal.
However, Chidambaram et al. do not disclose the metal being titanium, nickel, cobalt, or platinum.
Liang et al. et al. disclose silicide regions 154 and 254 (see Fig. 9) are formed using thin metal film such as Ni, Pt, Pd, Ti or Co and heated to case Si and Ge to react with metal layer to form germano-silicide layer (see Paragraph [0030]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Chidambaram et al. reference with metal layer such as titanium, nickel, cobalt, or platinum as taught by Liang et al. in order to form germano-silicide layer thereby the metal contact resistance can be reduced.
Re Claim 17, Chidambaram et al. disclose a method of processing a substrate comprising: positioning a substrate into a processing chamber, the substrate comprising: a n-channel metal-oxide semiconductor (NMOS) device; and a p-channel metal-oxide semiconductors (PMOS) device (see Fig. 2A); selectively depositing, with an epitaxial process in the processing chamber, a seed layer (224) over an NMOS source/drain region of the NMOS device and over a PMOS source/drain region of the PMOS device, the seed layer comprising both silicon and germanium (see Paragraph [0034]); forming, in the processing chamber and after depositing the seed layer, a metal silicide simultaneously over the NMOS source/drain and the PMOS source region, the seed layer being consumed during the forming of the metal silicide, the metal silicide comprising silicon and germanium and at least one metal (see Figs. 1-2k and related text in Paragraphs [0030]-[0040]).
However, Chidambaram et al. do not disclose the metal being titanium, nickel, cobalt, or platinum.
Liang et al. et al. disclose silicide regions 154 and 254 (see Fig. 9) are formed using thin metal film such as Ni, Pt, Pd, Ti or Co and heated to case Si and Ge to react with metal layer to form germano-silicide layer (see Paragraph [0030]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Chidambaram et al. reference with metal layer such as titanium, nickel, cobalt, or platinum as taught by Liang et al. in order to form germano-silicide layer thereby the metal contact resistance can be reduced.
Re Claim 18, as applied to claim 17 above, Chidambaram et al. and Liang et al. in combination disclose all the claimed limitations including wherein the seed layer is an un-doped silicon and germanium layer.
Re Claim 19, as applied to claim 17 above, Chidambaram et al. and Liang et al. in combination disclose all the claimed limitations including wherein forming metal silicide is a thermal process.
Re Claim 20, as applied to claim 17 above, Chidambaram et al. and Liang et al. in combination disclose all the claimed limitations including wherein forming metal silicide is a selective reaction process, the selective reaction process reacting only with the seed layer to form the metal silicide.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram et al. (US 2005/0139872) in view of Mitsuda et al. (US 2004/0132249).
Re Claim 8, as applied to claim 1 above, Chidambaram et al. disclose all the claimed limitations. However, Chidambaram et al. do not disclose a contact metal layer is deposited after the deposition of the metal silicide and on the metal silicide.
Mitsuda et al. disclose forming of contact metal layer (19) after formation of silicide layer (15), see Figs. 1 and 13, in order to form metallization layer (see Paragraph [0159]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Chidambaram et al. reference with a contact metal layer is deposited after the deposition of the metal silicide and on the metal-silicide as taught by Mitsuda et al. in order to form metallization layer (i.e., wiring layer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Koontz (US 7,279,406) discloses CMOS device that includes SiGe seed layer and silicide layer in the NMOS and PMOS regions.
Correspondence
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
August 17, 2026
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