DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Status of the Claims
Amendment filed March 24, 2026 is acknowledged. Claim 2, 9 and 16 have been amended. Claims 2-21 are pending.
Action on merits of claims 2-21 follows.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 16 and 19 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by YANG et al. (US. Pub. No. 2008/0174008).
With respect to claim 16, YANG teaches a method as claimed including:
forming a first interconnect structure (6) over a first side of a substrate, the substrate comprising a first via (8); (FIG. 5a)
bonding a first die (10) to the first interconnect structure (6); (FIG. 5b)
exposing the first via (8) on a second side of the substrate;
after bonding the first die (10), forming a second interconnect structure (20) over a second side of the substrate opposite the first side, the second interconnect structure (20) including a conductive line and an insulating layer (24) over the conductive line; (FIG. 5c)
bonding a second die (26) to the second interconnect structure (20);
forming an encapsulant (30) over the second interconnect structure (20) and the second die (26); (FIG. 5d); and
forming a through via (44) extending through the encapsulant (30) and the insulating layer (24) to the conductive line (20), wherein a surface of the encapsulant (30) distal from the second interconnect structure (20) is level with a surface of the through via (44) distal from the second interconnect structure (20). (See FIGs. 5a-e).
With respect to claim 19, a surface (upper) of the through via (44) is level with a surface (upper) of the encapsulant (30).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17-18 and 20-21 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over YANG ‘008 as applied to claim 16 above, and further in view of SAVASTIOUK et al. (US. Pub. No. 2005/0136635) of record.
With respect to claim 17, YANG teaches the method as describe in claim 16 above including: exposing the first via (8) on the second side of the substrate.
Thus, YANG is shown to teach all the features of the claim with the exception of explicitly disclosing exposing the first via including exposing a sidewall of the first via.
However, SAVASTIOUK teaches a method including:
forming a first interconnect structure (136) over a first side of a substrate (140), the substrate comprising a first via (430); (FIG. 7)
bonding a first die (124) to the first interconnect structure (136); (FIG. 15, step 1550)
exposing the first via (430) on a second side of the substrate, (FIG. 8, step 1560),
wherein exposing the first via (340) comprises exposing a sidewall of the first via (340).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to expose the first via of YANG comprising exposing the sidewall of the first via as taught by SAVASTIOUK to effectively reducing the thickness of the substrate.
With respect to claim 18, forming the second interconnect structure (20) of YANG comprises forming an insulating layer (24) over the second side of the substrate, wherein a surface (lower) of the insulating layer (24) is level with a surface (upper) of the first via (8).
With respect to claim 20, in view of SAVASTIOUK, the method further comprises a liner (430.1) between the first via (430.2) and the substrate (140), wherein the liner (430.2) is recessed back from an end of the first via (430.2).
With respect to claim 21, in view of HIGASHI, the first via (430.2) protrudes from the first side of the substrate.
Claims 2-3 and 5-8 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over OHTA et al. (US. Patent No. 7,102,085) of record, in view of SAVASTIOUK ‘635, and YANG ‘008.
With respect to claim 2, OHTA teaches a method of forming a device substantially as claimed including:
forming a conductive via (45) penetrating from a front side (42) of a substrate (41) and into the substrate;
forming a first interconnect structure (BU1) over the front side (42) of the substrate;
bonding a first die (68) onto the first interconnect structure (BU1);
after bonding the first die (68), expose an exposed end of the conductive via (45) such that the conductive via (45) forms a through-substrate via (TSV);
forming a second interconnect structure (BU2) on backside (43) of the substrate and electrically coupled to the exposed end (47) of the TSV, wherein forming the second interconnect structure (BU2) comprises:
forming a first insulating layer (49) on the backside (43) of the substrate, wherein the exposed end (47) of the TSV is exposed;
after forming the first insulating layer (49), forming a conductive line (53) over the first insulating layer (49), wherein the conductive line (53) directly contacts the TSV;
forming a second insulating layer (55) over the conductive line (53); and
forming a under-bump metallurgy (UBM 57) extending through the second insulating layer (55), the UBM (57) being electrically coupled to the conductive line (53).
bonding a second die (69) onto the second interconnect structure (BU2), wherein the second die (69) is electrically coupled to the UBM (57); (See FIG. 7).
Thus, OHTA is shown to teach all the features of the claim with the exception of explicitly disclosing removing a backside of the substrate to expose an exposed end of the conductive via; forming an encapsulant over the second die; and forming electrical connections through the encapsulant and the second insulating layer to the conductive line.
However, SAVASTIOUK teaches a method of forming a device including:
after bonding the first die (124, step 1550), removing a backside of substrate (140, step 1560) to expose an exposed end (340) of conductive via (330) such that the conductive via (330) forms a through-substrate via (TSV); and
forming a second interconnect structure (110) on the backside of the substrate (140) and electrically coupled to the exposed end (340) of the TSV (330). (See FIGs. 7-8 and 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to expose the exposed end of the conductive via of OHTA by removing the backside of the substrate as taught by SAVASTIOUK to reduce the thickness of the interposer, thus overall thickness of the package can be reduced.
Further, YANG teaches a method of forming a device including:
forming an encapsulant (30) over a second die (26); and
forming electrical connections (44) through the encapsulant (30) and second insulating layer (24) to the conductive line (20), wherein each of the electrical connections (44) has a surface that is level with a surface of the encapsulant (30), wherein the surface of the encapsulant (30) faces away from the second interconnect structure (20), wherein the surface of each of the electrical connections (44) face away from the second interconnect structure (20). (See FIGs. 3, 5e).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the device of OHTA including forming electrical connections through the encapsulant to the conductive line as taught by YANG so that more die can be added.
With respect to claim 3, in view of SAVASTIOUK, forming the conductive via (330) comprises forming a first dielectric layer (410) along sidewalls of a recess in the substrate (140) and forming a conductive material (420) over the first dielectric layer (410) in the recess.
With respect to claim 5, in view of SAVASTIOUK, the method further comprises etching the backside of the substrate (140) to expose a sidewall of the TSV.
With respect to claim 6, in view of YANG, the method further comprises forming a third interconnect structure (32) over the encapsulant (30) opposite the second interconnect structure (20).
With respect to claim 7, in view of YANG, the method further comprises forming an underfill (28) between the second die (26) and the second interconnect structure (20).
With respect to claim 8, the method of OHTA including forming a solder connection (67) on the UBM (57).
Claim 4 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over OHTA, SAVASTIOUK and YANG as applied to claim 3 above, and further in view of MATSUO (US. Pub. No. 2005/0029630) of record.
In view of SAVASTIOUK, forming the first interconnect structure over the front side of the substrate including: forming a second dielectric layer (144) over the front side of the substrate (140), wherein the second dielectric layer (144) is formed surrounding sidewalls of the first dielectric layer (410), wherein the first dielectric layer (410) comprises a first material, and wherein the second dielectric layer (144) comprises a second material different from the first material.
Thus, OHTA, SAVASTIOUK and YANG are shown to teach all the features of the claim with the exception of explicitly disclosing the second dielectric layer is formed surrounding and contacting sidewalls of the first dielectric layer.
However, MATSUO teaches a method of forming a device including:
forming a conductive via (20) penetrating from a front side (10a) of a substrate (10) and into the substrate; and
forming a first interconnect structure over the front side of the substrate (10),
wherein forming the first interconnect structure comprising forming a second dielectric layer (12/16) over the front side of the substrate,
wherein the second dielectric layer (12/16) is formed surrounding and contacting sidewalls of first dielectric layer (18), wherein the first dielectric layer (18) comprises a first material, and wherein the second dielectric layer (12/16) comprises a second material different from the first material (18). (See FIG. 5A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first interconnect structure of OHTA, in view of SAVASTIOUK, including the second dielectric layer being formed surrounding and contacting sidewalls of the first dielectric layer as taught by MATSUO for the same intended purpose of electrically isolating the first interconnect structure from the substrate.
Claims 9-15 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over SAVASTIOUK ‘635, in view of YANG ‘008.
With respect to claim 9, SAVASTIOUK teaches a method substantially as claimed including:
forming a first via (330) in a substrate (140);
forming a first interconnect structure over a first side (42) of the substrate;
attaching a first die (124.1) to the first interconnect structure; (step 1550);
after attaching the first die (124.1), thinning a second side (43) of the substrate (140) opposite the first side (42) of the substrate, the thinning exposing a first surface of the first via; (step 1560);
forming a second interconnect structure (110) over the second side (43) of the substrate. (See FIGs. 7, 8, 10 and 15).
Thus SAVASTIOUK is shown to teach all the features of the claim with the exception of explicitly disclosing attaching a second die to the second interconnect structure.
However, YANG teaches a method including:
attaching a second die (26) to second interconnect structure (20);
forming an encapsulant (30) over the second die (26) and the second interconnect structure (20); (FIG. 5d); and
after forming the encapsulant (30), forming a second via (44) through the encapsulant (30) to a conductive feature of the second interconnect structure (20), wherein a surface of the encapsulant (30) and a surface of the second via (44) are substantially coplanar. (See FIGs. 3, 5d-e).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the device of SAVASTIOUK including attaching the second die to the second interconnect structure as taught by YANG to providing a multiple chip module.
With respect to claim 10, thinning the second side (43) of the substrate (140) of SAVASTIOUK exposes a sidewall of the first via.
With respect to claim 11, in view of YANG, the method further comprises forming an insulating layer (24) on second side of the substrate, wherein a surface of the insulating layer (24) is level with a surface of first via (8).
With respect to claim 12, in view of YANG, the method further comprises, prior to forming the encapsulant (30), forming an underfill (28) between the second die (26) and the second interconnect structure (20).
With respect to claim 13, in view of YANG, the method further comprises:
forming a third interconnect structure (32) over the encapsulant (30); and
forming external connections (BUMPS) on the third interconnect structure (32).
With respect to claim 14, in view of YANG, the second die (26) is attached to the second interconnect structure (20) using solder joints.
With respect to claim 15, the first via (330) of SAVASTIOUK comprises a liner (430) and a conductive element, wherein the liner is recessed from an end of the conductive element. (FIG. 8).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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