DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Status of the Claims
Application filed July 29, 2024 as a Divisional of U.S. Application 18/525,966, is acknowledged. New claim 2-21 has been added. Claim 1 has been cancelled. Claims 2-21 are pending.
Action on merits of claims 2-21 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 29, 2024 and December 03, 2024 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
METHOD OF FORMING A 3D STACKED CHIP INCLUDING FORMING A FIRST DIE ON ONE SIDE OF A THROUGH-SUBSTRATE VIA (TSV) AND FORMING A SECOND DIE ON OPPOSITE SIDE OF THE TSV AFTER THINNING OF THE SUBSTRATE TO EXPOSE THE TSV
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 5-8 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over OHTA et al. (US. Patent No. 7102,085) in view of HIGASHI et al. (US. Pub. No. 20040262735) and SAVASTIOUK et al. (US. Pub. No. 2005/0136635) all of record.
With respect to claim 2, OHTA teaches a method of forming a device substantially as claimed including:
forming a conductive via (45) penetrating from a front side (42) of a substrate (41) and into the substrate;
forming a first interconnect structure (BU1) over the front side (42) of the substrate;
bonding a first die (68) onto the first interconnect structure (BU1);
after bonding the first die (68), expose an exposed end of the conductive via (45) such that the conductive via (45) forms a through-substrate via (TSV);
forming a second interconnect structure (BU2) on backside (43) of the substrate and electrically coupled to the exposed end (47) of the TSV, wherein forming the second interconnect structure (BU2) comprises:
forming a first insulating layer (49) on the backside (43) of the substrate, wherein the exposed end (47) of the TSV is exposed;
after forming the first insulating layer (49), forming a conductive line (53) over the first insulating layer (49), wherein the conductive line (53) directly contacts the TSV;
forming a second insulating layer (55) over the conductive line (53); and
forming a under-bump metallurgy (UBM 57) extending through the second insulating layer (55), the UBM (57) being electrically coupled to the conductive line (53).
bonding a second die (69) onto the second interconnect structure (BU2), wherein the second die (69) is electrically coupled to the UBM (57); (See FIG. 7).
Thus, OHTA is shown to teach all the features of the claim with the exception of explicitly disclosing removing a backside of the substrate to expose an exposed end of the conductive via; forming an encapsulant over the second die; and forming electrical connections through the encapsulant and the second insulating layer to the conductive line.
However, SAVASTIOUK teaches a method of forming a device including:
after bonding the first die (124, step 1550), removing a backside of substrate (140, step 1560) to expose an exposed end (340) of conductive via (330) such that the conductive via (330) forms a through-substrate via (TSV); and
forming a second interconnect structure (110) on the backside of the substrate (140) and electrically coupled to the exposed end (340) of the TSV (330). (See FIGs. 7-8 and 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to expose the exposed end of the conductive via of OHTA by removing the backside of the substrate as taught by SAVASTIOUK to reduce the thickness of the interposer, thus overall thickness of the package can be reduced.
Further, HIGASHI teaches a method of forming a device including:
forming an encapsulant (32b) over a second die (12); and
forming electrical connections (36) through the encapsulant (32b) to the conductive line (22b). (See FIG. 3b).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the device of OHTA including forming electrical connections through the encapsulant to the conductive line as taught by HIGASHI so that more die can be added.
With respect to claim 3, in view of SAVASTIOUK, forming the conductive via (330) comprises forming a first dielectric layer (410) along sidewalls of a recess in the substrate (140) and forming a conductive material (420) over the first dielectric layer (410) in the recess.
With respect to claim 5, in view of SAVASTIOUK, the method further comprises etching the backside of the substrate (140) to expose a sidewall of the TSV.
With respect to claim 6, in view of HIGASHI, the method further comprises forming a third interconnect structure (36) over the encapsulant (32b) opposite the second interconnect structure.
With respect to claim 7, in view of HIGASHI, the method further comprises forming an underfill between the second die (12) and the second interconnect structure.
With respect to claim 8, OHTA teaches forming a solder connection (67) on the UBM (57).
Claim 4 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over OHTA, HIGASHI and SAVASTIOUK as applied to claim 3 above, and further in view of MATSUO (US. Pub. No. 2005/0029630) of record.
In view of SAVASTIOUK, forming the first interconnect structure over the front side of the substrate including: forming a second dielectric layer (144) over the front side of the substrate (140), wherein the second dielectric layer (144) is formed surrounding sidewalls of the first dielectric layer (410), wherein the first dielectric layer (410) comprises a first material, and wherein the second dielectric layer (144) comprises a second material different from the first material.
Thus, OHTA, HIGASHI and SAVASTIOUK are shown to teach all the features of the claim with the exception of explicitly disclosing the second dielectric layer is formed surrounding and contacting sidewalls of the first dielectric layer.
However, MATSUO teaches a method of forming a device including:
forming a conductive via (20) penetrating from a front side (10a) of a substrate (10) and into the substrate, wherein forming the conductive via (20) comprises forming a first dielectric layer (18) along sidewalls of a recess (H3) in the substrate (10) and forming a conductive material (20) over the first dielectric layer (18) in the recess; and
forming a first interconnect structure over front side (10a) of substrate (10), wherein forming the first interconnect structure over the front side of the substrate including:
forming a second dielectric layer (12) over the front side (10a) of the substrate (10), wherein the second dielectric layer (12) is formed surrounding and contacting sidewalls of first dielectric layer (18), wherein the first dielectric layer (18) comprises a first material, and wherein the second dielectric layer (12) comprises a second material different from the first material. (See FIG. 5A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first interconnect structure of OHTA, in view of SAVASTIOUK, including the second dielectric layer being formed surrounding and contacting sidewalls of the first dielectric layer as taught by MATSUO for the same intended purpose of electrically isolating the first interconnect structure from the substrate.
Claims 9-10 and 12-15 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over SAVASTIOUK ‘635, in view of HIGASHI ‘735.
With respect to claim 9, SAVASTIOUK teaches a method substantially as claimed including:
forming a first via (330) in a substrate (140);
forming a first interconnect structure over a first side (42) of the substrate;
attaching a first die (124.1) to the first interconnect structure; (step 1550);
after attaching the first die (124.1), thinning a second side (43) of the substrate (140) opposite the first side (42) of the substrate, the thinning exposing a first surface of the first via; (step 1560);
forming a second interconnect structure (110) over the second side (43) of the substrate. (See FIGs. 7, 8, 10 and 15).
Thus SAVASTIOUK is shown to teach all the features of the claim with the exception of explicitly disclosing attaching a second die to the second interconnect structure.
However, HIGASHI teaches a method including:
forming a second interconnect structure (22b) over second side of substrate (20);
attaching a second die (12) to the second interconnect structure (22b);
forming an encapsulant (32b) over the second die (12) and the second interconnect structure (22b); and
after forming the encapsulant (32b), forming a second via through the encapsulant (32b) to a conductive feature of the second interconnect structure. (See FIGs. 1d-e, 3a-b).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the device of SAVASTIOUK including attaching the second die to the second interconnect structure as taught by HIGASHI to providing a multiple chip module.
With respect to claim 10, thinning the second side (43) of the substrate (140) of SAVASTIOUK exposes a sidewall of the first via.
With respect to claim 12, in view of HIGASHI, the method further comprises, prior to forming the encapsulant, forming an underfill (13) between the second die (12) and the second interconnect structure.
With respect to claim 13, in view of HIGASHI, the method further comprises:
forming a third interconnect structure (22c) over the encapsulant (32b); and
forming external connections (44) on the third interconnect structure. (FIG. 3c).
With respect to claim 14, in view of HIGASHI, the second die (12) is attached to the second interconnect structure using solder joints.
With respect to claim 15, the first via (330) of SAVASTIOUK comprises a liner (430) and a conductive element, wherein the liner is recessed from an end of the conductive element. (FIG. 8).
Claim 11 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over SAVASTIOUK and HIGASHI as applied to claim 9 above, and further in view of ECHIGO et al. (US. Patent No. 6,274,821) of record.
The method of SAVASTIOUK and HIGASHI further comprises forming an insulating layer on the second side (43) of the substrate (140), wherein the insulating layer having a surface.
Thus, SAVASTIOUK and HIGASHI are shown to teach all the features of the claim with the exception of explicitly disclosing the surface of the insulating layer is level with a surface of the first via.
However, EICHIGO teaches a method including:
forming a first via (5) in a substrate (1);
forming a first interconnect structure (2) over a first side of the substrate (1);
forming an insulating layer (L4i) on the second side of the substrate (1), wherein a surface of the insulating layer (L4i) is level with a surface of the first via (5). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the surface of the insulating layer of SAVASTIOUK being level with a surface of the first via as taught by EICHIGO for the same intended purpose of electrically isolating the substrate from the interconnect structure.
Claim 16-17 and 19-21 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over SAVASTIOUK ‘635, HIGASHI ‘735 and EICHELBERGER (US. Patent No. 5,111,278) of record.
With respect to claim 16, SAVASTIOUK teaches a method substantially as claimed including:
forming a first interconnect structure over a first side (42) of a substrate (140), the substrate comprising a first via (330);
bonding a first die (124) to the first interconnect structure;
exposing the first via (330) on a second side (43) of the substrate;
after bonding the first die (124), forming a second interconnect structure (110) over a second side (43) of the substrate opposite the first side (42), the second interconnect structure (110) including a conductive line (910) and an insulating layer (110.2) over the conductive line (910). (See FIGs. 7, 8, 10, 15).
Thus SAVASTIOUK is shown to teach all the features of the claim with the exception of explicitly disclosing bonding a second die to the second interconnect structure.
However, HIGASHI teaches a method including:
forming a second interconnect structure (22b) over second side of substrate (20);
bonding a second die (12) to the second interconnect structure (22b);
forming an encapsulant (32b) over the second die (12); and
forming a through via extending through the encapsulant (32b) to the conductive line. (See FIGs. 3a-b).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the device of SAVASTIOUK including attaching the second die to the second interconnect structure as taught by HIGASHI to providing a multiple chip module.
Thus, SAVASTIOUK, in view of HIGASHI, is shown to teach all the features of the claim with the exception of explicitly disclosing forming the through via extending through the encapsulant and the insulating layer to the conductive line.
However, EICHELBERGER teaches a method including:
forming a second interconnect structure over second side of substrate (30), the second interconnect structure including a conductive line (34) and an insulating layer (40) over the conductive line (34);
bonding a second die (38) to the second interconnect structure;
forming an encapsulant (42) over the second die (38); and
forming a through via (43) extending through the encapsulant (42) and the insulating layer (40) to the conductive line (34). (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the through via of SAVASTIOUK, in view of HAGASHI, extending through the encapsulant and the insulating layer to the conductive line as taught by EICHELBERGER to provide electrical contact to the conductive line.
With respect to claim 17, exposing the first via (330) of SAVASTIOUK comprises exposing a sidewall of the first via.
With respect to claim 19, in view of EICHELBERGER a surface of the through via (43) is level with a surface of the encapsulant (42).
With respect to claim 20, the method of SAVASTIOUK further comprises a liner (430) between the first via (330) and the substrate (140), wherein the liner (430) is recessed back from an end of the first via (330).
With respect to claim 21, in view of HIGASHI, the first via (28) protrudes from the first side of the substrate.
Claim 18 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over SAVASTIOUK, HIGASHI and EICHELBERGER, as applied to claim 17 above, and further in view of ECHIGO ‘821.
forming the second interconnect structure of SAVASTIOUK comprises forming an insulating layer (940/110) over the second side (43) of the substrate (140), wherein the insulating layer having a surface.
Thus, SAVASTIOUK, HIGASHI and EICHELBERGER are shown to teach all the features of the claim with the exception of explicitly disclosing the surface of the insulating layer is level with a surface of the first via.
However, EICHIGO teaches a method including:
forming a first via (5) in a substrate (1);
forming a first interconnect structure (2) over a first side of the substrate (1);
forming an insulating layer (L4i) on the second side of the substrate (1), wherein a surface of the insulating layer (L4i) is level with a surface of the first via (5). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the surface of the insulating layer of SAVASTIOUK being level with a surface of the first via as taught by EICHIGO for the same intended purpose of electrically isolating the substrate from the interconnect structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893