DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11,742,210 in view of Park et al, US Patent 6,093,641 and Chung et al, US Patent 8,609,497
Regarding claim 1, USP11742210 recites the limitations of a method, comprising: receiving a workpiece comprising (column 12, line 1):
a structure over a substrate (column 12, lines 1);
a first gate structure over a first channel region of a structure (column 12, line 2-3),
a second gate structure over a second channel region of the structure (column 12, lines 3-4),
a source/drain feature over a source/drain region between the first channel region and the second channel region (column 12, lines 5-7);
conformally depositing a dielectric layer over a top surface of the source/drain feature (column 12, lines 8-12);
after the conformally depositing, anisotropically etching the dielectric layer to expose the source/drain feature (column 12, lines 13-14);
performing an implantation process to the dielectric layer (column 12, line 15 ); and
after the performing of the implantation process, performing a pre-clean process to the workpiece, wherein the implantation process comprises a non-zero tilt angle (column 12, lines 17-20).
USP11742210 fails to recite the structure is a fin structure, a first gate-top dielectric layer over the first gate structure, a first gate spacer extending along sidewalls of the first gate structure and the first gate-top dielectric layer, a second gate-top dielectric layer over the second gate structure, a second gate spacer extending along sidewalls of the second gate structure and the second gate-top dielectric layer, and depositing a dielectric layer along sidewalls of the first gate spacer and the second gate spacer;
However, Park teaches a first gate-top dielectric layer 21c over the first gate structure and a second gate-top dielectric layer 21c over the second gate structure, (figure 2a) as gate caps, which are generally used in the art to prevent etching of the underlying gate electrode in subsequent manufacturing processing. Further, Park teaches a first gate spacer 21d extending along sidewalls of the first gate structure and the first gate-top dielectric layer, a second gate spacer 21d extending along sidewalls of the second gate structure and the second gate-top dielectric layer, and depositing a dielectric layer 22 along sidewalls of the first gate spacer and the second gate spacer. Gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with that of USP11742210 because gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device and gate caps are generally used in the art to prevent etching of the underlying gate electrode in subsequent manufacturing processing.
USP11742210 and Park fail to teach the structure is a fin structure.
Chung teaches the structure is a fin structure (column 4, lines 35-38) as an alternative, yet generally-known types of transistors that are used in a semiconductor component. FinFets are used in semiconductor components to reduce current from leaking and increase power efficiency.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chung with that of USP11742210 and Park because FinFets are used in semiconductor components to reduce current from leaking and increase power efficiency.
Regarding claim 2, USP11742210 recites the limitation dielectric layer comprises silicon nitride, silicon carbonitride, or silicon (claim 2).
Regarding claim 3, USP11742210 recites the limitation the implantation process comprises use of xenon or argon (claim 3).
Regarding claim 4, USP11742210 recites the limitation the non-zero tilt angle is between about 10° and about 85° (claim 4).
Regarding claim 5, USP11742210 recites the limitation the implantation process causes oxidation of the dielectric layer to form an oxidized portion of the dielectric layer, wherein the pre-clean process removes the oxidized portion of the dielectric layer (claim 5).
Regarding claim 6, USP11742210 recites the limitation the implantation process causes damages to the dielectric layer to form a damaged portion of the dielectric layer, wherein the pre-clean process removes the damaged portion of the dielectric layer (claim 6).
Regarding claim 7, USP11742210 recites the limitation before the implantation process, performing a pre-silicide implantation process to the workpiece, wherein the pre-silicide implantation process implants exposed source/drain feature with germanium (claim 7).
Regarding claim 8, USP11742210 recites the limitation the pre-silicide implantation process comprises a zero-degree tilt angle (claim 8).
Claims 9-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-20 of U.S. Patent No. 11,742,210 in view of Park et al, US Patent 6,093,641.
Regarding claim 9, USP11742210 recites the limitation of a method, comprising:
receiving a workpiece comprising (column 12, line 47)
a first gate structure (column 12, line 48),
a second gate structure (column 12, line 49),
a source/drain opening between the first gate spacer and the second gate spacer (column 12, lines 52-51); and
a source/drain feature exposed in the source/drain opening (column 12, lines 52-53);
conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature (column 12, lines 54-56);
anisotropically etching the dielectric layer to expose the source/drain feature (column 12, lines 57-58);
performing a first implantation process to the exposed source/drain feature (column 12, lines 59-60);
after the performing of the first implantation process, performing a second implantation process to the dielectric layer to form a treated portion (column 12, lines 61-63); and
after the performing of the second implantation process, performing a pre-clean process to the workpiece (column 12, lines 64-65),
wherein the pre-clean process etches the treated portion faster than it does the dielectric layer (column 12, lines 66-67).
USP11742210 fails to recite a first gate-top dielectric layer over the first gate structure, a first gate spacer extending along sidewalls of the first gate structure and the first gate-top dielectric layer, a second gate-top dielectric layer over the second gate structure, and a second gate spacer extending along sidewalls of the second gate structure and the second gate-top dielectric layer.
However, Park teaches a first gate-top dielectric layer 21c over the first gate structure and a second gate-top dielectric layer 21c over the second gate structure (figure 2a) as gate caps, which are generally used in the art to prevent etching of the underlying gate electrode in subsequent manufacturing processing. Further, Park teaches a first gate spacer 21c extending along sidewalls of the first gate structure and the first gate-top dielectric layer and a second gate spacer 21c extending along sidewalls of the second gate structure and the second gate-top dielectric layer. Gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with that of USP11742210 because gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device and gate caps are generally used in the art to prevent etching of the underlying gate electrode in subsequent manufacturing processing.
Regarding claim 910, USP11742210 recites the limitation of the conformally depositing of the dielectric layer forms accumulation of the dielectric layer around an edge of the source/drain opening (claim 10).
Regarding claim 11, USP11742210 recites the limitation of the treated portion includes the accumulation of the dielectric layer around the edge of the source/drain opening (claim 10).
Regarding claim 12, USP11742210 recites the limitation of the pre-clean process comprises use of hydrofluoric acid, ammonia, or water (claim 11).
Regarding claim 13, USP11742210 recites the limitation of the dielectric layer comprises silicon nitride, silicon carbonitride, or silicon (claim 12).
Regarding claim 14, USP11742210 recites the limitation of the first implantation process comprises use of germanium, and wherein the second implantation process comprises use of xenon or argon (claim 13).
Regarding claim 15, USP11742210 recites the limitation of the first implantation process comprises a zero-degree tilt angle, wherein the second implantation process comprises a non-zero tilt angle (claim 14).
Regarding claim 16, USP11742210 recites the limitation of an ion beam energy of the second implantation process is greater than an ion beam energy of the first implantation process (claim 15).
Regarding claim 17, USP11742210 recites the limitation of an implantation dosage the second implantation process is greater than an implantation dosage of the first implantation process (claim 16).
Regarding claim 18, USP11742210 recites the limitations of a method, comprising:
receiving a workpiece comprising a source/drain feature exposed between two gate structures column 14, lines 1-2, wherein the gate spacer is part of the gate structure);
conformally depositing a dielectric layer over a top surface of the source/drain feature and along sidewalls of the two gate spacers to define a source/drain opening between the two gate spacers (column 14, lines 3-6);
after the conformally depositing, anisotropically etching the dielectric layer to expose the source/drain feature (column 14, lines 7-8);
performing an implantation process to the dielectric layer to form a treated portion of the dielectric layer (column 14, lines 9-10);
after the performing of the implantation process, performing a pre-clean process to the workpiece (column 14, lines 11-12);
forming a silicide layer over the source/drain feature (column 14, line 13); and
forming a metal plug over the silicide layer, wherein the implantation process implants xenon or argon (column 14, lines 14-16), wherein the implantation process comprises a non-zero tilt angle (claim 1, column 12, lines 19-20).
USP11742210 fails to recite the gate structures include gate spacers.
However, Park teaches that gate spacers 21d are part of the gate structure 21 (figure 2a). Gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with that of USP11742210 because gate spacers are generally-used in a gate structure to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
Regarding claim 19, USP11742210 recites the limitations after the anisotropically etching of the dielectric layer, the source/drain opening comprises a necking profile, wherein the pre-clean process reduces the necking profile by removing the treated portion (claim 19).
Regarding claim 20, USP11742210 recites the limitations forming of the silicide layer comprises: depositing a metal precursor over the workpiece; annealing the workpiece to bring about silicidation between the metal precursor and the source/drain feature to form the silicide layer; and removing the metal precursor along the sidewalls of the source/drain opening (claim 20).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights