DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over An(USPGPUB DOCUMENT: 2020/0411507, hereinafter An) in view of Pan(USPGPUB DOCUMENT: 2020/0006186, hereinafter Pan).
Re claim 1 An discloses in Fig 2 a method of forming a semiconductor arrangement, comprising: forming a device layer(layer of STR) in a substrate(1); wherein forming the first heat conductor comprises: forming a first dummy metal layer(214); forming a first dummy vertical interconnect access (VIA) layer(226) over the first dummy metal layer(214); and forming a second dummy metal layer(236) over the first dummy Via layer(226).
An does not disclose forming a first metal layer over the device layer(layer of STR); forming a first dummy metal layer(214) over the first metal layer; forming a first heat conductor over the first metal layer,
Pan discloses in Fig 1, 4, 5 a first metal layer(134) over the device layer(124/126); forming a first heat conductor(STR) (130/132) over the first metal layer,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pan to the teachings of An in order to improved heat transfer capabilities [0004, Pan]. In doing so, forming a first dummy metal layer(214) over the first metal layer(134 of Pan);
Re claim 2 An and Pan disclose the method of claim 1, comprising: bonding an upper surface of a dummy interconnect structure of the second dummy metal layer(236) to a heat sink.
Re claim 3 An and Pan disclose the method of claim 2, wherein bonding the upper surface of the dummy interconnect structure of the second dummy metal layer(236) to the heat sink comprises: forming a bonding layer (bond pads)[0006,0042 of Pan] of aluminum nitride over the upper surface of the dummy interconnect structure; and bonding a surface of the heat sink to the upper surface of the dummy interconnect structure of the second dummy metal layer(236) using the bonding layer (bond pads)[0006,0042 of Pan].
Re claim 4 An and Pan disclose the method of claim 1, comprising: forming a heat source(STR) over the first metal layer, wherein forming the first heat conductor comprises forming the first heat conductor over the heat source(STR).
Re claim 5 An and Pan disclose the method of claim 4, comprising: forming a second heat conductor prior to forming the heat source(STR), wherein forming the heat source(STR) comprises forming the heat source(STR) over the second heat conductor.
Re claim 6 An and Pan disclose the method of claim 4, wherein forming the heat source(STR) comprises forming a resistor.
Re claim 7 An and Pan disclose the method of claim 1, wherein forming the first heat conductor comprises: forming a third dummy metal layer(214) overlying the first dummy Via layer(226) before forming the second dummy metal layer(236).
Re claim 8 An and Pan disclose the method of claim 7, wherein forming the first heat conductor comprises: forming a second dummy Via layer(226) overlying the third dummy metal layer(214) before forming the second dummy metal layer(236), wherein forming the second dummy metal layer(236) comprises forming the second dummy metal layer(236) to overlie the third dummy metal layer(214).
Re claim 9 An and Pan disclose the method of claim 1, comprising: forming a second metal layer under the device layer(layer of STR).
Re claim 10 An discloses in Fig 2 a method of forming a semiconductor arrangement, comprising: forming a heat source(STR);
An does not disclose forming a first heat conductor overlying the heat source(STR); forming a bonding layer overlying the first heat conductor; and bonding a heat sink to the bonding layer.
Pan discloses in Fig 1, 4, 5 forming a first heat conductor(112) overlying the heat source(130/132); forming a bonding layer (bond pads)[0006,0042 of Pan] overlying the first heat conductor; and bonding a heat sink(108) to the bonding layer(bond pads)[0006,0042].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pan to the teachings of An in order to improved heat transfer capabilities [0004, Pan].
Re claim 11 An and Pan disclose the method of claim 10, wherein: forming the heat source(STR) comprises forming the heat source(STR) on a substrate(1); and the method comprises removing a portion of the substrate(1) after bonding the heat sink to the bonding layer (bond pads)[0006,0042 of Pan].
Re claim 12 An and Pan disclose the method of claim 11, comprising: forming a metal layer on a remaining portion of the substrate(1) after removing the portion of the substrate(1).
Re claim 13 An and Pan disclose the method of claim 10, wherein: forming the heat source(STR) comprises forming the heat source(STR) on a device layer(layer of STR), and the method comprises forming a first metal layer over the device layer(layer of STR) prior to forming the heat source(STR).
Re claim 14 An and Pan disclose the method of claim 13, comprising: forming a second metal layer on an opposite side of device layer(layer of STR) relative to the first metal layer.
Re claim 15 An and Pan disclose the method of claim 10, wherein forming the heat source(STR) comprises forming a resistor.
Re claim 16 An and Pan disclose the method of claim 10, wherein forming the bonding layer (bond pads)[0006,0042 of Pan] comprises forming an aluminum nitride layer.
Re claim 17 An discloses in Fig 2 a method of forming a semiconductor arrangement, comprising: forming a heat source(STR) over a substrate(1); and forming a via layer(226) on an opposite side of the substrate(1) relative to the heat source(STR) after removing the portion of the substrate(1).
An does not disclose forming a heat conductor overlying the heat source(STR); disposing a heat sink over the heat conductor; removing a portion of the substrate(1) after forming the heat conductor;
Pan discloses in Fig 1, 4, 5 forming a heat conductor(112) overlying the heat source(130/132); disposing a heat sink(108) over the heat conductor(112);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pan to the teachings of An in order to improved heat transfer capabilities [0004, Pan]. In doing so, removing a portion of the substrate(1) after forming the heat conductor(112 of Pan);
Re claim 18 An and Pan disclose the method of claim 17, wherein removing the portion of the substrate(1) comprises removing the portion of the substrate(1) after disposing the heat sink over the heat conductor.
Re claim 19 An and Pan disclose the method of claim 17, comprising: forming a metal layer on the opposite side of the substrate(1) relative to the heat source(STR) prior to forming the via layer(226).
Re claim 20 An and Pan disclose the method of claim 17, comprising forming a dielectric layer on the via layer(226) such that the via layer(226) is between the substrate(1) and the dielectric layer.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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