DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 4-10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4-6 and 9-12 of U.S. Patent No. 12,125,748. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in the instant application have already been recited in USP12125748
Regarding claim 1, claims 9-11 of USP12125748 recites the limitation of a semiconductor structure, comprising:
an active region comprising a channel region and a source/drain region (column 13, lines 39-41);
a source/drain feature over the source/drain region (column 13, line 42);
a gate structure over the channel region (column 13, line 43 or 44);
a first etch stop layer over the source/drain feature (column 13, line 45-47);
a first dielectric layer over the first etch stop layer (column 13, line 48);
a second etch stop layer over the first dielectric layer and the first etch stop layer (column 13, line 49-51);
a second dielectric layer over the second etch stop layer (column 13, line 52); and
a source/drain contact comprising (column 13, line 53):
a lower portion extending through the first etch stop layer and the first dielectric layer (column 13, line 54-55) and
an upper portion disposed on the lower portion, the upper portion extending through the second etch stop layer and the second dielectric layer (column 13, line 56-58),
wherein a bottom surface of the upper portion comprises a first width and a top surface of the lower portion comprises a second width smaller than the first width (claims 11-12).
Regarding claim 4, USP12125748 recites the limitation of the lower portion tapers toward the source/drain feature, wherein the upper portion tapers toward the lower portion (claim 11).
Regarding claim 5, USP12125748 recites the limitation of a first metal liner disposed between the lower portion and the first dielectric layer (claim 13, lines 59-60); and a second metal liner disposed between the upper portion and the second dielectric layer (claim 13, lines 64-65), wherein a composition of the first metal liner is different from a composition of the second metal liner (column 13, line 66-column 14, line 4).
Regarding claim 6, USP12125748 recites the limitation of the first metal liner comprises tantalum (Ta) and tantalum nitride (TaN), a mixture of cobalt (Co) and cobalt nitride (CoN), a mixture of nickel (Ni) and nickel nitride (NiN), or a mixture of tungsten (W) and tungsten nitride (WN), wherein the second metal liner comprises tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide (column 13, line 66-column 14, line 4).
Regarding claim 7, USP12125748 recites the limitation of the source/drain contact comprises: a first metal layer in direct contact with the first metal liner and the second metal liner; and a second metal layer spaced apart from the first metal liner and the second metal liner by the first metal layer (claim 3).
Regarding claim 8, USP12125748 recites the limitation of the first metal layer comprises ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W), wherein the second metal layer comprises copper (Cu), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W) (claim 4).
Regarding claim 9, USP12125748 recites the limitation of a silicide feature disclosed between the lower portion and the source/drain feature (claim 5).
Regarding claim 10, USP12125748 recites the limitation of the silicide feature comprises titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide (claim 6).
Claims 2-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,125,748 in view of Jangjian et al, US Patent 9,620,610
Regarding claims 2-3, USP12125749 fails to recite a gate spacer extending along a sidewall of the gate structure, wherein the first etch stop layer extends along a sidewall of the gate spacer.
Jangjian teaches a gate spacer 322a extending along a sidewall of the gate structure 340/342/344/346/348/350, wherein the first etch stop layer 320 extends along a sidewall of the gate spacer (figure 3G). Gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jangjian with that of USP12125748because gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-14 of U.S. Patent No. 12,125,748 in view of Jiangjian et al, US Patent 9,620,610
Regarding claim 11, claim 9 of USP12125748 recites the limitation of a semiconductor structure, comprising:
an active region having a source/drain region sandwiched between a first channel region and a second channel region (column 13, lines 39-41);
a source/drain feature over the source/drain region (column 13, line 42);
a first gate structure over the first channel region (column 13, line 43);
a second gate structure over the second channel region (column 13, line 44);
a first etch stop layer extending along a sidewall of the first gate, over the source/drain feature, and along a sidewall of the second gate (column 13, lines 45-47);
a first dielectric layer over the first etch stop layer (column 13, line 48);
a second etch stop layer over the first dielectric layer, the first etch stop layer, the first gate structure, and the second gate structure a second dielectric layer over the second etch stop layer (column 13, line 49-51);
a source/drain contact comprising (column 13, line 53):
a lower portion extending through the first etch stop layer and the first dielectric layer (column 13, line 54-55); and
an upper portion disposed on the lower portion, the upper portion extending through the second etch stop layer and the second dielectric layer (column 13, line 56-58);
a first metal liner disposed between the lower portion and the first dielectric layer (column 13, lines 59-60); and
a second metal liner disposed between the upper portion and the second dielectric layer (column 13, line 64-65).
USP12125748 fails to recite the limitation of a first gate spacer disposed along a sidewall of the first gate structure; a second gate spacer disposed along a sidewall of the second gate structure; the first etch stop layer extending along a sidewall of the first gate spacer and along a sidewall of the second gate spacer
However Jangjian teaches a first gate spacer 322a disposed along a sidewall of the first gate structure 340/342/344/346/348/350; a second gate spacer 322b disposed along a sidewall of the second gate structure 340/342/344/346/348/350; the first etch stop layer 320 extending along a sidewall of the first gate spacer and along a sidewall of the second gate spacer (figure 3G). Gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jangjian with that of USP12125748because gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
Regarding claim 12, USP12125748 recites the limitation of the first metal liner comprises tantalum and tantalum nitride, a mixture of cobalt and cobalt nitride, a mixture of nickel and nickel nitride, or a mixture of tungsten and tungsten nitride, wherein the second metal liner comprises tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide (column 13, line 66 to column 14, line 4).
Regarding claim 13, USP12125748 recites the limitation of a silicide feature disclosed between the lower portion and the source/drain feature, wherein the silicide feature comprises titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide (claim 10).
Regarding claim 14, USP12125748 recites the limitation of the lower portion tapers toward the source/drain feature, wherein the upper portion tapers toward the lower portion (claim 11).
Regarding claim 15, USP12125748 recites the limitation of a bottom width of the upper portion is greater than a top width of the lower portion (claim 12).
Regarding claim 16, USP12125748 recites the limitation of the bottom width is between about 14 nm and about 16 nm, wherein the top width is between about 13 nm and about 15 nm (claim 13).
Regarding claim 17, USP12125748 recites the limitation of a dielectric barrier layer sandwiched between the first metal liner and the first dielectric layer, wherein the dielectric barrier layer comprises silicon nitride (claim 14).
Allowable Subject Matter
Claims 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, the prior art fails to anticipate or render obvious the claimed invention including “...the source/drain contact comprises a step-wise width change at an interface between the lower portion and the upper portion...” in combination with the remaining limitations. Claims 19-20 are dependent upon claim 18 and are therefore allowable.
Regarding claim 18, claims of USP12,125,748 recites the limitation of a semiconductor structure, comprising:
a fin structure (column 14, line 32) having a source/drain region sandwiched between a first channel region and a second channel region (column 13, lines 39-41);
a source/drain feature over the source/drain region (column 13, line 42);
a first gate structure over the first channel region (column 13, line 43);
a second gate structure over the second channel region (column 13, line 44);
a first etch stop layer extending along a sidewall of the first gate, over the source/drain feature, and along a sidewall of the second gate (column 13, line 45-47);
a first dielectric layer over the first etch stop layer (column 13, lines 48);
a second etch stop layer over the first dielectric layer, the first etch stop layer, the first gate structure, and the second gate structure a second dielectric layer over the second etch stop layer (column 13, lines 49-51); and
a source/drain contact comprising (column 13, line 53):
a lower portion extending through the first etch stop layer and the first dielectric layer (column 13, line 54-55), and
an upper portion disposed on the lower portion, the upper portion (column 13, line 56-58),
USP12125748 fails to recite a first gate spacer disposed along a sidewall of the first gate structure; a second gate spacer disposed along a sidewall of the second gate structure; the first etch stop layer extending along a sidewall of the first gate spacer, a second etch stop layer over the first etch stop layer, and the source/drain contact comprises a step-wise width change at an interface between the lower portion and the upper portion.
USP12125748 fails to recite the limitation of a first gate spacer disposed along a sidewall of the first gate structure; a second gate spacer disposed along a sidewall of the second gate structure; the first etch stop layer extending along a sidewall of the first gate spacer and along a sidewall of the second gate spacer
However Jangjian teaches a first gate spacer 322a disposed along a sidewall of the first gate structure 340/342/344/346/348/350; a second gate spacer 322b disposed along a sidewall of the second gate structure 340/342/344/346/348/350; the first etch stop layer 320 extending along a sidewall of the first gate spacer, and a second etch stop layer 320 over the first etch stop layer (figure 3G). Gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jangjian with that of USP12125748because gate spacers are generally-used in the art to further isolate the gate electrode from a source/drain contact, thereby preventing electrical shortening of the electronic device.
USP12125748 and Jangjian fail to teach the source/drain contact comprises a step-wise width change at an interface between the lower portion and the upper portion. After further search, no other prior art was found that would meet the limitations of these claims, either in anticipatory or in combination with other references. Therefore, claims 18-20 have been found to be allowable.
Conclusion
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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