Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement filed July 29, 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. After reviewing the supplied documents in parent application 17/658232, Examiner finds there has been no upload of the cited “Search Report for German Application No. 10 2022 108 561.9”. Therefore it has been placed in the application file, but the information referred to therein has not been considered.
The information disclosure statement filed August 3, 2026 was filed is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Semiconductor Devices With Sequentially Stacked Metallization And Non-Conducting Layers Including Corrosion Prevention Implant—
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The claims cite an “active circuit” but the specification fails to provide a definition of this term nor exact examples. Paragraph [0003] states that elements which “conduct signals for operation of circuitry included in the semiconductor device” is an example of “active circuitry”. Paragraph [0050] and Fig. 4 identifies an “active circuitry layer” within the context of the device structure, but does not reference an active circuit.
Without a clear reference, it is not clear what the intent of the limitation “active circuit” means.
Claim Objections
Claims 1, 6, 10, and 14 are objected to because of the following informalities:
Regarding Claims 1, 6, and 10, the limitation “separating the second metallization layer into a first portion and second portion” should read --separating the second metallization layer into a first portion and a second portion--
Regarding Claim 14, the limitation “The method of claim 10, comprising” should read --the method of claim 10, further comprising--
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1, 2, 6, 7, 10, 11, and 15-17, the claims recite the limitation of an “active circuit”. As was mentioned in the Specification section above, this is provided no limiting definition in the disclosure nor is the term identified with any particular element of the structures provided. As such, it’s unclear as to what the claimed structure is and what could be identified as an active circuit. This also runs into interpretation issues of whether electricity needs to be present and whether possible current flow must be restricted therein (closed).
Regarding Claims 3-5, the claims are rejected based on their dependence on Claim 1.
Regarding Claims 8-9, the claims are rejected based on their dependence on Claim 6.
Regarding Claims 12-14, the claims are rejected based on their dependence on Claim 10.
Regarding Claims 18-19, the claims are rejected based on their dependence on Claim 1.
For the purpose of this Office Action, the Examiner will interpret the limitation “active circuit” as being directed to simply a layer containing elements which provide electrical conductivity, as is understood of Applicant’s ‘active circuitry layer’ ((412); Fig. 4, Paragraph [0050])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2022/0122898), hereinafter Chen, in view of Cabral, JR. et al. (U.S. Pub. 2006/0084256; cited on IDS dated July 29, 2024), hereinafter Cabral, Jr.
Regarding Claim 1, Chen teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) comprising:
-a semiconductor substrate ((102); Fig. 18, Paragraph [0017]);
-an active circuit (comprising (112), and contacts (108) and (106), hereinafter (AC); Fig. 18, Paragraphs [0019], [0021], and [0025]) disposed on a surface of the semiconductor substrate (top of (102); Fig. 18);
-a first metallization layer ((136) and (138); Fig. 18, Paragraph [0039]) disposed on the active circuit (AC), the first metallization layer ((136) and (138)) including a first through hole (e.g. as between the two center portions, hereinafter (H1), see also Fig. 13);
-a first non-conducting layer ((142); Fig. 18, Paragraph [0040]) disposed on the first metallization layer ((136) and (138)) and in the first through hole (H1), the first non-conducting layer (142) including a second through hole (e.g. center-right (144); Fig. 15, Paragraph [0041]);
-a second metallization layer ((146) and (148); Fig. 18, Paragraph [0042]) disposed on the first non-conducting layer (142) and in the second through hole (center-right (144)), the second metallization layer ((146) and (148)) including a third through hole (e.g. as between the right and center portions, hereinafter (H3), see also Fig. 16) separating the second metallization layer into a first portion and a second portion (right and center-right portions of (146) and (148), respectively);
-a second non-conducting layer ((152); Fig. 18, Paragraph [0043]) disposed on the second metallization layer ((146) and (148)) and in the third through hole (H3), the second non-conducting layer (152) including a fourth through hole (e.g. center (154); Fig. 18, Paragraph [0046]) above the second portion of the second metallization layer (center-right portion of (146) and (148)),
-the fourth through hole (154) exposing (e.g. no (152) directly above) at least a portion of the upper surface of the second metallization layer. (See Fig. 18)
Chen does not explicitly teach:
-a corrosion prevention implant disposed in an upper surface of the second metallization layer;
Cabral, Jr. teaches a semiconductor device (Figs. 1-3, Paragraph [0019]) wherein:
-a corrosion prevention implant ((24); Fig. 2, Paragraphs [0023] and [0025]) disposed in an upper surface of a metallization layer ((12); Fig. 2, Paragraph [0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cabral, Jr. into the device of Chen such that it includes a corrosion prevention implant disposed in an upper surface of the second metallization layer. This would be due to the fact that doing so would protects against contaminants and improves contact adhesion (Cabral, Jr., Paragraph [0025]).
Regarding Claim 2, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 1, wherein:
-the active circuit (AC) includes at least one electrical contact (e.g. right (106) and (108); Fig. 18).
Regarding Claim 3, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 1, wherein:
-the first portion of the second metallization layer (right portion of (146) and (148)) is electrically coupled with the semiconductor substrate (102) via an electrical contact (right (106) and (108)).
Regarding Claim 4, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 1, wherein:
-at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls (e.g. fourth through hole, Center (154); Fig. 18).
Regarding Claim 5, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 1, further comprising:
-a connector (e.g. center (160); Fig. 19, Paragraph [0047]) electrically coupled to the upper surface of the second metallization layer (top of (146) and (148)).
Regarding Claim 6, Chen teaches a silicon carbide semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) comprising:
-a silicon carbide substrate ((102); Fig. 18, Paragraph [0017]);
-an active circuit (comprising (112), and contacts (108) and (106), hereinafter (AC); Fig. 18, Paragraphs [0019], [0021], and [0025]) disposed on a surface of the silicon carbide substrate (top of (102); Fig. 18);
-a first metallization layer ((136) and (138); Fig. 18, Paragraph [0039]) disposed on the active circuitry layer (AC), the first metallization layer ((136) and (138)) including a first through hole (e.g. as between the two center portions, hereinafter (H1), see also Fig. 13);
-a first non-conducting layer ((142); Fig. 18, Paragraph [0040]) disposed on the first metallization layer ((136) and (138)) and in the first through hole (H1), the first non-conducting layer (142) including a second through hole (e.g. center-right (144); Fig. 15, Paragraph [0041]);
-a second metallization layer ((146) and (148); Fig. 18, Paragraph [0042]) disposed on the first non-conducting layer (142) and in the second through hole (center-right (144)), the second metallization layer ((146) and (148)) including a third through hole (e.g. as between the right and center portions, hereinafter (H3), see also Fig. 16) separating the second metallization layer into a first portion and a second portion (right and center-right portions of (146) and (148), respectively);
-a second non-conducting layer ((152); Fig. 18, Paragraph [0043]) disposed on the second metallization layer ((146) and (148)) and in the third through hole (H3), the second non-conducting layer (152) including a fourth through hole (e.g. center (154); Fig. 18, Paragraph [0046]) above the second portion of the second metallization layer (center-right portion of (146) and (148)),
-the fourth through hole (154) exposing (e.g. no (152) directly above) at least a portion of the upper surface of the second metallization layer. (See Fig. 18)
Chen does not explicitly teach:
-a corrosion prevention implant disposed in an upper surface of the second metallization layer;
Cabral, Jr. teaches a semiconductor device (Figs. 1-3, Paragraph [0019]) wherein:
-a corrosion prevention implant ((24); Fig. 2, Paragraphs [0023] and [0025]) disposed in an upper surface of a metallization layer ((12); Fig. 2, Paragraph [0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cabral, Jr. into the device of Chen such that it includes a corrosion prevention implant disposed in an upper surface of the second metallization layer. This would be due to the fact that doing so would protects against contaminants and improves contact adhesion (Cabral, Jr., Paragraph [0025]).
Regarding Claim 7, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 6, wherein:
-the active circuit (AC) includes at least one electrical contact (e.g. right (106) and (108); Fig. 18).
Regarding Claim 8, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 6, wherein:
-the first portion of the second metallization layer (right portion of (146) and (148)) is electrically coupled with the semiconductor substrate (102) via an electrical contact (right (106) and (108)).
Regarding Claim 9, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 6, wherein:
-at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls (e.g. fourth through hole, Center (154); Fig. 18).
Regarding Claim 10, Chen teaches a method for producing a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]), the method comprising:
-forming an active circuit (comprising (112), and contacts (108) and (106), hereinafter (AC); Figs. 3 and 18, Paragraphs [0019], [0021], and [0025]) on a surface of a semiconductor substrate ((102); Fig. 3 and 18, Paragraph [0017]);
-forming a first metallization layer ((136) and (138); Figs. 13 and 18, Paragraph [0039]) on the active circuit (AC), the first metallization layer ((136) and (138)) including a first through hole (e.g. as between the two center portions, hereinafter (H1), see also Fig. 13);
-forming a first non-conducting layer ((142); Figs. 14 and 18, Paragraph [0040]) on the first metallization layer ((136) and (138)) and in the first through hole (H1), the first non-conducting layer (142) including a second through hole (e.g. center-right (144); Fig. 15, Paragraph [0041]);
-forming a second metallization layer ((146) and (148); Figs. 16 and 18, Paragraph [0042]) on the first non-conducting layer (142) and in the second through hole (center-right (144)), the second metallization layer ((146) and (148)) including a third through hole (e.g. as between the right and center portions, hereinafter (H3), see also Fig. 16) separating the second metallization layer into a first portion and a second portion (right and center-right portions of (146) and (148), respectively);
-forming a second non-conducting layer ((152); Fig. 18, Paragraph [0043]) disposed on the second metallization layer ((146) and (148)) and in the third through hole (H3), the second non-conducting layer (152) including a fourth through hole (e.g. center (154); Fig. 18, Paragraph [0046]) above the second portion of the second metallization layer (center-right portion of (146) and (148)),
-the fourth through hole (154) exposing (e.g. no (152) directly above) at least a portion of the upper surface of the second metallization layer. (See Fig. 18)
Chen does not explicitly teach:
-a corrosion prevention implant disposed in an upper surface of the second metallization layer;
Cabral, Jr. teaches a method of forming a semiconductor device (Figs. 1-3, Paragraph [0019]) wherein:
-forming a corrosion prevention implant ((24); Fig. 2, Paragraphs [0023] and [0025]) disposed in an upper surface of a metallization layer ((12); Fig. 2, Paragraph [0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cabral, Jr. into the method of Chen such that it includes a corrosion prevention implant disposed in an upper surface of the second metallization layer. This would be due to the fact that doing so would protects against contaminants and improves contact adhesion (Cabral, Jr., Paragraph [0025]).
Regarding Claim 11, Chen as modified by Cabral, Jr. teaches a method for producing a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 10, wherein:
-forming the active circuit (AC) includes forming at least one electrical contact (e.g. right (106) and (108); Fig. 18) of the active circuit (AC).
Regarding Claim 12, Chen as modified by Cabral, Jr. teaches a method for producing a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 10, wherein:
-forming an electrical contact (right (106) and (108)) electrically coupling the first portion of the second metallization layer (right portion of (146) and (148)) with the semiconductor substrate (102).
Regarding Claim 13, Chen as modified by Cabral, Jr. teaches a method for producing a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 10, wherein:
-at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls (e.g. fourth through hole, Center (154); Fig. 18).
Regarding Claim 14, Chen as modified by Cabral, Jr. a method for producing a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 10, further comprising:
-electrically coupling a connector (e.g. center (160); Fig. 19, Paragraph [0047]) to the upper surface of the second metallization layer (top of (146) and (148)).
Regarding Claim 15, Chen teaches a semiconductor device assembly having an active circuit embedded in the semiconductor device assembly (Figs. 1-19; Paragraphs [0014]-[0016]) comprising:
-a semiconductor substrate (comprising (102), (112), and contacts (108) and (106), hereinafter (SUB); Fig. 18, Paragraphs [0017], [0019], [0021], and [0025]) including an active circuit ((112), and contacts (108) and (106), hereinafter (AC));
-a first metallization layer ((136) and (138); Fig. 18, Paragraph [0039]) disposed on the active circuit (AC) of the semiconductor substrate (SUB);
-a first non-conducting layer ((142); Fig. 18, Paragraph [0040]) disposed on the first metallization layer ((136) and (138));
-a second metallization layer ((146) and (148); Fig. 18, Paragraph [0042]) disposed on the first non-conducting layer (142);
-a second non-conducting layer ((152); Fig. 18, Paragraph [0043]) disposed on the second metallization layer ((146) and (148)), the second non-conducting layer (152) including a through hole (e.g. center (154); Fig. 18, Paragraph [0046]) exposing (e.g. no (152) directly above) at least a portion of the upper surface of the second metallization layer. (See Fig. 18)
Chen does not explicitly teach:
-a corrosion prevention implant disposed in an upper surface of the second metallization layer;
Cabral, Jr. teaches a semiconductor device (Figs. 1-3, Paragraph [0019]) wherein:
-a corrosion prevention implant ((24); Fig. 2, Paragraphs [0023] and [0025]) disposed in an upper surface of a metallization layer ((12); Fig. 2, Paragraph [0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cabral, Jr. into the device of Chen such that it includes a corrosion prevention implant disposed in an upper surface of the second metallization layer. This would be due to the fact that doing so would protects against contaminants and improves contact adhesion (Cabral, Jr., Paragraph [0025]).
Regarding Claim 16, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 15, further comprising:
-an external connector (e.g. center (160); Fig. 19, Paragraph [0047]) that is electrically coupled with the active circuit (AC) via the first metallization layer ((136) and (138)) and the second metallization layer ((146) and (148)).
Regarding Claim 17, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 15, wherein:
-the active circuit (AC) includes at least one electrical contact (e.g. right (106) and (108); Fig. 18).
Regarding Claim 18, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 15, wherein:
-the second metallization layer ((146) and (148)) is electrically coupled with the semiconductor substrate (SUB) via an electrical contact (e.g. right (106) and (108)).
Regarding Claim 19, Chen as modified by Cabral, Jr. teaches a semiconductor device (Figs. 1-19; Paragraphs [0014]-[0016]) of Claim 15, wherein:
-the through hole includes tapered side walls (Center (154); Fig. 18).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Pub. 2021/0118829: Discloses a semiconductor device (e.g. (100), Fig. 1H-1) including an active circuit ((134) and (132)), a first metallization layer ((242), (244), etc.), a first non-conducting layer (250), a second metallization layer (270), and a second non-conducting layer (260), with other claimed limitations.
U.S. Pub. 2019/0115312: Discloses a semiconductor device (e.g. (110), Fig. 3) including an active circuit ((12) and (13)), a first metallization layer (15), a first non-conducting layer (31), a second metallization layer (21), and a second non-conducting layer (41), with other claimed limitations.
U.S. Pub. 2017/0374748: Discloses a semiconductor device (e.g. (18), Fig. 1G) including an active circuit ((120) and (120P)), a first metallization layer (110), a first non-conducting layer (208), a second metallization layer (210), and a second non-conducting layer (112), with other claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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