DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/29/2024, 10/7/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 3, 7 and 15-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-5, 10, 13 and 15-18 of U.S. Patent No. 11,239,208. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '208 discloses, in claims 1, 2, 4, and 5, a device, comprising: a first integrated circuit die including: a first device layer having a first transistor structure; a first front-side interconnect structure on a front-side of the first device layer; and a first backside interconnect structure on a backside of the first device layer, the first backside interconnect structure including a first dielectric layer and a first backside via extending through the first dielectric layer to a first source/drain region of the first transistor structure; a second integrated circuit die including: a second device layer having a second transistor structure; a second front-side interconnect structure on a front-side of the second device layer; and a second backside interconnect structure on a backside of the second device layer; and wherein the first integrated circuit die and the second integrated circuit die are bonded together using one of: front-to-front bonding between the first and second front-side interconnect structures, back-to-front bonding between the first backside interconnect structure and the second front-side interconnect structure, or back-to-back bonding between the first and second backside interconnect structures ("a device comprising: a first integrated circuit device comprising: a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure comprising: a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device comprising: a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, wherein the first interconnect structure is bonded to the front-side interconnect structure by dielectric-to- dielectric and metal-to-metal bonds", “the first interconnect structure is disposed on a front-side of the second device layer”, and “a second interconnect structure disposed on a backside of the second device layer, the second interconnect structure comprising: a second dielectric layer on the backside of the second device layer; and a second contact extending through the second dielectric layer to a source/drain region of the second transistor structure”, in claims 1, 2, and 4 of Pat '208, are interpreted as the same limitation); wherein at least one of the first or second backside interconnect structures includes a backside power rail electrically coupled to a respective source/drain region through a respective backside via ("the backside interconnect structure comprises a first backside power rail electrically coupled to the source/drain region of the first transistor structure through the first contact, and wherein the second interconnect structure comprises a second backside power rail electrically coupled to the source/drain region of the second transistor structure through the second contact", in claim 5 of Pat '208, is interpreted as the same limitation).
Regarding claim 3, Pat '208 discloses the device of claim 1 as described above.
Pat '208 does not explicitly disclose the first backside interconnect structure further comprises a passivation layer, under-bump metallizations (UBMs), and external connectors.
Pat '208 teaches, in claim 13, the first backside interconnect structure further comprises a passivation layer, under-bump metallizations (UBMs), and external connectors ("the second integrated circuit device further comprises: a passivation layer on a surface of the third interconnect structure opposite the second device layer; an underbump metallization (UBM) in the passivation layer; and an external connector on the UBM, the external connector being electrically coupled to the third interconnect structure through the UBM", in claim 13 of Pat '208, is interpreted as the same limitation), for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 1-2 and 4-5 of Pat '208 to have the first backside interconnect structure further comprising a passivation layer, under-bump metallizations (UBMs), and external connectors, as taught by claim 13 of Pat '208, for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Regarding claim 7, Pat '208 discloses the device of claim 1 as described above.
Pat '208 does not explicitly disclose the backside via is electrically coupled to the respective source/drain region through a silicide region.
Pat '208 teaches, in claim 10, the backside via is electrically coupled to the respective source/drain region through a silicide region ("the first backside via is electrically coupled to the first source/drain region through a first silicide region", in claim 10 of Pat '208, is interpreted as the same limitation), for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 1-2 and 4-5 of Pat '208 to have the backside via being electrically coupled to the respective source/drain region through a silicide region, as taught by claim 13 of Pat '208, for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Regarding claim 15, Pat '208 discloses, in claims 15, 16, and 17, A method, comprising: forming a first integrated circuit die having a first transistor structure; forming a second integrated circuit die having a second transistor structure; forming a backside interconnect structure on a backside of at least one of the first or second integrated circuit dies, including: forming backside vias electrically coupled to source/drain regions of respective transistor structures; and forming conductive lines electrically connected to the backside vias; bonding the first integrated circuit die to the second integrated circuit die to form a heterogeneous integrated circuit package; and wherein at least one of the backside vias and conductive lines comprises backside power delivery to its respective integrated circuit die ("a method comprising: forming a first transistor on a first substrate; forming a first interconnect structure over the first transistor; exposing a first source/drain region of the first transistor, wherein exposing the first source/drain region comprises thinning the first substrate; after exposing the first source/drain region, forming a second interconnect structure over the first transistor opposite the first interconnect structure, wherein forming the second interconnect structure comprises: depositing a first dielectric layer over the first transistor; forming a first backside via through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor; and forming a first conductive line electrically connected to the first backside via; and bonding a first integrated circuit device to the first interconnect structure, wherein bonding the first integrated circuit device to the first interconnect structure comprises forming dielectric-to-dielectric bonds between the first integrated circuit device and the first interconnect structure", “forming the first integrated circuit device, wherein forming the first integrated circuit device comprises: forming a second transistor on a second substrate; and forming a third interconnect structure over the second transistor opposite the second substrate, wherein bonding the first integrated circuit device to the first interconnect structure comprises forming the dielectric-to-dielectric bonds between the third interconnect structure and the first interconnect structure”, and “forming the third interconnect structure comprises forming a second conductive line over and electrically coupled to the second transistor, wherein the first conductive line is a first power rail, and wherein the second conductive line is a second power rail”, in claims 15, 16, and 17 of Pat '208, are interpreted as the same limitation).
Regarding claim 16, Pat '208 discloses the method of claim 15 as described above.
Pat '208 further discloses, in claim 18, forming the backside interconnect structure comprises: thinning a substrate of the respective integrated circuit die to expose source/drain regions; depositing a dielectric layer over the exposed source/drain regions; forming the backside vias through the dielectric layer; and forming the conductive lines over the dielectric layer and in electrical contact with the backside vias ("forming the first integrated circuit device, wherein forming the first integrated circuit device comprises: forming a second transistor on a second substrate; exposing a second source/drain region of the second transistor, wherein exposing the second source/drain region comprises thinning the second substrate; and after exposing the second source/drain region, forming a third interconnect structure over the second transistor, wherein forming the third interconnect structure comprises: depositing a second dielectric layer over the second transistor; forming a second backside via through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor; and forming a second conductive line electrically connected to the second backside via", in claim 18 of Pat '208, is interpreted as the same limitation).
Regarding claim 17, Pat '208 discloses the method of claim 15 as described above.
Pat '208 further discloses, in claim 16, bonding the first integrated circuit die to the second integrated circuit die comprises dielectric-to-dielectric bonds and metal-to-metal bonds ("forming the first integrated circuit device, wherein forming the first integrated circuit device comprises: forming a second transistor on a second substrate; and forming a third interconnect structure over the second transistor opposite the second substrate, wherein bonding the first integrated circuit device to the first interconnect structure comprises forming the dielectric-to-dielectric bonds between the third interconnect structure and the first interconnect structure", in claim 16 of Pat '208, is interpreted as the same limitation).
Regarding claim 18, Pat '208 discloses the method of claim 15 as described above.
Pat '208 does not explicitly disclose forming a front-side interconnect structure on a front-side of at least one of the first or second integrated circuit dies.
Pat '208 teaches, in claim 1, forming a front-side interconnect structure on a front-side of at least one of the first or second integrated circuit dies ("a front-side interconnect structure on a front-side of the first device layer", in claim 1 of Pat '208, is interpreted as the same limitation), for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 15-17 of Pat '208 to have the forming a front-side interconnect structure on a front-side of at least one of the first or second integrated circuit dies, as taught by claim 1 of Pat '208, for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Claims 2, 5-6, 8-10, 12-14 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-5, 13 and 15-17 of U.S. Patent No. 11,239,208 in view of Huang (US 2021/0335690).
Regarding claim 2, Pat '208 discloses the device of claim 1 as described above.
Pat '208 does not explicitly disclose the first transistor structure comprises a nanostructure field-effect transistor (nano-FET).
Huang teaches, in at least figures 29A-29C and related text, the device comprising the first transistor structure comprises a nanostructure field-effect transistor (nano-FET) ([6]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Pat '208 and Huang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '208 with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '208 to have the first transistor structure comprising a nanostructure field-effect transistor (nano-FET), as taught by Huang, for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11], Huang).
Regarding claim 5, Pat '208 discloses the device of claim 1 as described above.
Pat '208 does not explicitly disclose the first backside interconnect structure further comprises an embedded passive device.
Huang teaches, in at least figures 29A-29C and related text, the device comprising the first backside interconnect structure further comprises an embedded passive device (140, [86]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Pat '208 and Huang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '208 with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '208 to have the first backside interconnect structure further comprising an embedded passive device, as taught by Huang, for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11], Huang).
Regarding claim 6, Pat '208 in view of Huang discloses the device of claim 5 as described above.
Huang further teaches, in at least figures 29A-29C and related text, the embedded passive device is a metal-insulator-metal (MIM) inductor ([86]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Regarding claim 8, Pat '208 discloses, in claims 1, 2, 4, and 5, A device, comprising: a first integrated circuit die including: a first device layer having first transistor structures; a first front-side interconnect structure on a front-side of the first device layer; and a first backside interconnect structure on a backside of the first device layer; a second integrated circuit die including: a second device layer having second transistor structures; a second front-side interconnect structure on a front-side of the second device layer; and a second backside interconnect structure on a backside of the second device layer; wherein the first integrated circuit die and the second integrated circuit die are stacked and bonded together; wherein at least one of the first or second backside interconnect structures includes backside power rails electrically connected to source/drain regions of respective transistor structures through backside vias ("a device comprising: a first integrated circuit device comprising: a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure comprising: a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device comprising: a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, wherein the first interconnect structure is bonded to the front-side interconnect structure by dielectric-to- dielectric and metal-to-metal bonds", “the first interconnect structure is disposed on a front-side of the second device layer”, “a second interconnect structure disposed on a backside of the second device layer, the second interconnect structure comprising: a second dielectric layer on the backside of the second device layer; and a second contact extending through the second dielectric layer to a source/drain region of the second transistor structure”, and "the backside interconnect structure comprises a first backside power rail electrically coupled to the source/drain region of the first transistor structure through the first contact, and wherein the second interconnect structure comprises a second backside power rail electrically coupled to the source/drain region of the second transistor structure through the second contact", in claims 1, 2, 4, and 5 of Pat '208, are interpreted as the same limitation).
Pat '208 does not explicitly disclose the first front-side interconnect structure includes first front-side power rails electrically connected to source/drain regions or gate structures of the first transistor structures.
Huang teaches, in at least figures 29A-29C and related text, the device comprising the first front-side interconnect structure includes first front-side power rails electrically connected to source/drain regions or gate structures (102/100, [60]) of the first transistor structures (115, [67]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Pat '208 and Huang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '208 with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '208 to have the first front-side interconnect structure including first front-side power rails electrically connected to source/drain regions or gate structures of the first transistor structures, as taught by Huang, for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11], Huang).
Regarding claim 9, Pat '208 in view of Huang discloses the device of claim 8 as described above.
Pat '208 further discloses, in claim 1, the first and second integrated circuit dies are bonded together dielectric-to-dielectric bonds and metal-to-metal bonds ("the first interconnect structure is bonded to the front-side interconnect structure by dielectric-to- dielectric and metal-to-metal bonds ", in claim 1 of Pat '208, is interpreted as the same limitation).
Regarding claim 10, Pat '208 in view of Huang discloses the device of claim 8 as described above.
Huang further teaches, in at least figures 29A-29C and related text, the first transistor structures comprise nanostructure field-effect transistors (nano-FETs) ([6]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Regarding claim 12, Pat '208 in view of Huang discloses the device of claim 8 as described above.
Huang further teaches, in at least figures 29A-29C and related text, at least one of the first or second backside interconnect structures includes an embedded passive device (140, [86]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Regarding claim 13, Pat '208 in view of Huang discloses the device of claim 8 as described above.
The claimed limitation of "the first integrated circuit die is a logic die and the second integrated circuit die is a memory die" has not patentable weight because it is interpreted as intended use.
Regarding claim 14, Pat '208 in view of Huang discloses the device of claim 8 as described above.
Pat '208 does not explicitly disclose at least one of the first or second backside interconnect structures further comprises a passivation layer, under-bump metallizations (UBMs), and external connectors.
Pat '208 teaches, in claim 13, at least one of the first or second backside interconnect structures further comprises a passivation layer, under-bump metallizations (UBMs), and external connectors ("the second integrated circuit device further comprises: a passivation layer on a surface of the third interconnect structure opposite the second device layer; an underbump metallization (UBM) in the passivation layer; and an external connector on the UBM, the external connector being electrically coupled to the third interconnect structure through the UBM", in claim 13 of Pat '208, is interpreted as the same limitation), for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 1-2 and 4-5 of Pat '208 to have at least one of the first or second backside interconnect structures further comprising a passivation layer, under-bump metallizations (UBMs), and external connectors, as taught by claim 13 of Pat '208, for the purpose of providing packaged semiconductor devices having IC dies which include backside power rails allows for the IC dies to be formed with greater transistor densities, reduces distances between bonded IC dies, and provides for greater flexibility in IC die stacking and packaging.
Regarding claim 20, Pat '208 discloses the method of claim 15 as described above.
Pat '208 does not explicitly disclose forming nanostructure field-effect transistors (nano-FETs).
Huang teaches, in at least figures 29A-29C and related text, the method comprising forming nanostructure field-effect transistors (nano-FETs) ([6]), for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11]).
Pat '208 and Huang are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '208 with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '208 to have the forming nanostructure field-effect transistors (nano-FETs), as taught by Huang, for the purpose of providing thermal conductive paths from a device that generates heat (e.g., a transistor, resistor, or the like) to an exterior of the chip, thereby allowing for improved heat dissipation and compensating for operating temperature increases ([11], Huang).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 4 that recite "the backside power rail has a width at least twice a width of a front-side power rail in the first front-side interconnect structure" in combination with other elements of the base claims 1 and 4.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 8 and 11 that recite "the backside power rails in the first backside interconnect structure have a greater width than the first front-side power rails in the first front-side interconnect structure" in combination with other elements of the base claims 8 and 11.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 15, 18, and 19 that recite "the conductive lines in the backside interconnect structure comprise backside power rails having a greater width than front-side power rails in the front-side interconnect structure" in combination with other elements of the base claims 15, 18, and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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