Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements filed 7/29/24 have been considered.
Oath/Declaration
Oath/Declaration filed on 7/29/24 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 9, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. Patent Publication No. 2018/0266437).
Referring to figures 2-13, Chen et al. teaches a semiconductor device, comprising: a semiconductor substrate (12) diced from a semiconductor wafer (10);
a first chiplet (20a) comprising a first circuit and a second chiplet (20b) comprising a second circuit, both of the first chiplet and second chiplet are disposed over the semiconductor substrate and are separated by a die-to-die space (38) filled with a dielectric material(40); and
a plurality of conductive connection patterns(56a) connecting the first circuit and the second circuit and disposed over the die-to-die space (see figure 7).
Regarding to claims 4, 13, further comprising one or more passivation layers covering the first circuit, the second circuit and the plurality of connection patterns (60, see figure 9).
Regarding to claims 5, 14, a mold resin encapsulating the semiconductor substrate with the first and second chiplets and the plurality of connection patterns (see paragraph# 54, figure 12-13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 6, 10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2018/0266437) applied to claims 1, 4-5, 9, 13-14 above, and further in view of Dabral et al. (U.S. Patent Publication No. 2018/0294230).
Referring to figures 2-13, Chen et al. teaches a semiconductor device, comprising: a semiconductor substrate (12) diced from a semiconductor wafer (10);
a first chiplet (20a) comprising a first circuit and a second chiplet (20b) comprising a second circuit, both of the first chiplet and second chiplet are disposed over the semiconductor substrate and are separated by a die-to-die space (38) filled with a dielectric material(40); and
a plurality of conductive connection patterns(56a) connecting the first circuit and the second circuit and disposed over the die-to-die space (see figure 7).
However, the reference does not specific teach the die-to-die space comprises no functional circuit electrically connected to at least one of the first circuit or the second circuit, other than the plurality of conductive connection patterns (in claim 3, 10); the plurality of conductive connection patterns connect patterns at an uppermost conductive layer of the first circuit and patterns at an uppermost conductive layer of the second circuit (in claim 6, 12).
Dabral et al. teaches the die-to-die space comprises no functional circuit electrically connected to at least one of the first circuit or the second circuit (108a/108b), other than the plurality of conductive connection patterns (see figures 1, 5, meeting claim 3, 10); the plurality of conductive connection patterns connect patterns at an uppermost conductive layer of the first circuit and patterns at an uppermost conductive layer of the second circuit (135/136, see figures 1, 5, meeting claim 6, 12).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was file would form the die-to-die space comprises no functional circuit electrically connected to at least one of the first circuit or the second circuit, other than the plurality of conductive connection patterns and the plurality of conductive connection patterns connect patterns at an uppermost conductive layer of the first circuit and patterns at an uppermost conductive layer of the second circuit in CHEN et al. as taught by Dabral et al. because it is known in the art to provide electrical connection to adjacent dies.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2018/0266437) applied to claims 1, 4-5, 9, 13-14 above, and further in view of Rubin et al. (U.S. Patent Publication No. 2021/0134724).
Referring to figures 2-13, Chen et al. teaches a semiconductor device, comprising: a semiconductor substrate (12) diced from a semiconductor wafer (10);
a first chiplet (20a) comprising a first circuit and a second chiplet (20b) comprising a second circuit, both of the first chiplet and second chiplet are disposed over the semiconductor substrate and are separated by a die-to-die space (38) filled with a dielectric material(40); and
a plurality of conductive connection patterns(56a) connecting the first circuit and the second circuit and disposed over the die-to-die space (see figure 7).
However, the reference does not the first chiplet differs in size from the second chiplet (in claim 8)
Rubin et al. teaches the first chiplet differs in size from the second chiplet (132/142, see figures 1-5).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the first chiplet differs in size from the second chiplet in Chen et al. as taught by Rubin et al. because it is known in the art to form different chiplet dimensions.
Claim(s) 2, 7, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2018/0266437), and further in view of Dabral et al. (U.S. Patent Publication No. 2018/0294230) as applied to claims 1, 3-6, 8-10, 12-14 above, and further in view of Wei et al. (U.S. Patent Publication No. 2017/0213798).
Referring to figures 2-13, Chen et al. teaches a semiconductor device, comprising: a semiconductor substrate (12) diced from a semiconductor wafer (10);
a first chiplet (20a) comprising a first circuit and a second chiplet (20b) comprising a second circuit, both of the first chiplet and second chiplet are disposed over the semiconductor substrate and are separated by a die-to-die space (38) filled with a dielectric material(40); and
a plurality of conductive connection patterns(56a) connecting the first circuit and the second circuit and disposed over the die-to-die space (see figure 7).
However, the reference does not teach the size of semiconductor substrate (in claims 2, 7 11).
Wei et al. teaches the size of semiconductor substrate (see paragraph# 44, figures 20-21).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the specific size of semiconductor substrate in Chen et al. as taught by Wei et al. because it is known in the art to form a large chip.
Claim(s) 15-16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (U.S. Patent Publication No. 20180294230), and further in view of Chen et al. (U.S. Patent Publication No. 2018/0266437).
Referring to figures 1-5, Dabral et al. teaches semiconductor device, comprising: first and second chiplets (110) over a semiconductor substrate (101), wherein the semiconductor substrate is diced from a semiconductor wafer, the first chiplet comprises a first circuit functionality and the second chiplet comprises a second circuit functionality; a third chiplet over the semiconductor substrate, wherein the third chiplet comprises a third circuit functionality (see figure 2a); and a plurality of conductive connection patterns connecting two or more of the first chiplet, the second chiplet, or the third chiplet and over a die-to-die space, wherein the first, second, and third chiplets are separated by the die-to-die space (see figure 2).
However, the reference does not clearly teach the die-to-die space is filled with a dielectric material.
Chen et al. teaches the die-to-die space is filled with a dielectric material (38/40, see figures 7-10).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the die-to-die space is filled with a dielectric material in Dabral et al. as taught by Chen et al. because it is known in the art to provide isolation and mechanical support in the region adjacent to dies while provide electrical connection.
Regarding to claim 16, the width of the die-to-die space is the same between each of the first, second, and third chiplets (see figure 2a).
Regarding to claim 18, fourth and fifth chiplets over the semiconductor substrate, wherein the fourth chiplet comprises the first circuit functionality and the fifth chiplet comprises the second circuit functionality (see figure 2a).
Regarding to claim 19, the first chiplet is aligned in a same row as the fourth chiplet and the second chiplet is aligned in a same row as the fifth chiplet (see figure 2a).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (U.S. Patent Publication No. 20180294230), and further in view of Chen et al. (U.S. Patent Publication No. 2018/0266437) as applied to claims 15-16, 18-19 above, and further in view of Wei et al. (U.S. Patent Publication No. 2017/0213798).
Referring to figures 1-5, Dabral et al. teaches semiconductor device, comprising: first and second chiplets (110) over a semiconductor substrate (101), wherein the semiconductor substrate is diced from a semiconductor wafer, the first chiplet comprises a first circuit functionality and the second chiplet comprises a second circuit functionality; a third chiplet over the semiconductor substrate, wherein the third chiplet comprises a third circuit functionality (see figure 2a); and a plurality of conductive connection patterns connecting two or more of the first chiplet, the second chiplet, or the third chiplet and over a die-to-die space, wherein the first, second, and third chiplets are separated by the die-to-die space (see figure 2).
However, the reference does not clearly teach the width of the die-to-die space between the first and second chiplet differs from the width of the die-to-die space between the second and third chiplet.
Wei et al. teaches the width of the die-to-die space between the first and second chiplet differs from the width of the die-to-die space between the second and third chiplet (see paragraph# 44, figures 20-21).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the specific size of semiconductor substrate in Dabral et al. as taught by Wei et al. because it is known in the art to form nonuniform spacing between adjacent chiplets/dies into the chip.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (U.S. Patent Publication No. 20180294230), and further in view of Chen et al. (U.S. Patent Publication No. 2018/0266437) as applied to claims 15-16, 18-19 above, and further in view of Crafts (U.S. Patent No. 6,489641).
Referring to figures 1-5, Dabral et al. teaches semiconductor device, comprising: first and second chiplets (110) over a semiconductor substrate (101), wherein the semiconductor substrate is diced from a semiconductor wafer, the first chiplet comprises a first circuit functionality and the second chiplet comprises a second circuit functionality; a third chiplet over the semiconductor substrate, wherein the third chiplet comprises a third circuit functionality (see figure 2a); and a plurality of conductive connection patterns connecting two or more of the first chiplet, the second chiplet, or the third chiplet and over a die-to-die space, wherein the first, second, and third chiplets are separated by the die-to-die space (see figure 2).
However, the reference does not clearly teach a row axis pitch of the first chiplet differs from the fourth chiplet.
Crafts teaches a row axis pitch of the first chiplet differs from the fourth chiplet (see figure 7).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form a row axis pitch of the first chiplet differs from the fourth chiplet in Dabral et al. as taught by Crafts et al. because it is known in the art to optimize lithographic exposure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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