Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“SEMICONDUCTOR DEVICES HAVING L-SHAPED ACTIVE REGIONS AND METHODS OF FORMING THE SAME”
Specification
The disclosure is objected to because of the following informalities:
The specification is objected to because paragraph [0050] contains an apparent grammatical error. Specifically, paragraph [0050] recites that “a spacer material is formed over both the first device region 106.” The use of “both” is inconsistent with the singular recitation of “the first device region 106” and renders the description unclear.
Appropriate correction is required.
The specification is objected to because paragraph [0060] contains an apparent incorrect reference numeral and/or inconsistent terminology. Specifically, paragraph [0060] refers to “dummy gates 72,” whereas the dummy gate structure described in the specification is identified using different reference numerals, including dummy gate electrode 121.
Applicant is required to clarify the identity of “dummy gates 72” and amend the specification to provide consistent terminology and reference numerals.
The specification is objected to because paragraph [0087] contains an apparent incorrect reference numeral. Specifically, paragraph [0087] refers to “substrate 100,” whereas the substrate is otherwise identified in the specification as substrate 101.
Applicant is required to correct or clarify the reference numeral so that the specification and drawings consistently identify the corresponding element.
The specification is objected to because paragraph [0088] contains a grammatical error. Specifically, paragraph [0088] recites “one ‘L-shaped’ active regions 301.” The singular modifier “one” is inconsistent with the plural noun “regions.”
Appropriate correction is required.
The specification is objected to because paragraph [0088] contains inconsistent references to the fins illustrated in FIG. 15B. Paragraph [0088] initially identifies a third fin 1525 and a fourth fin 1527 as components of the second cell scheme 1510. However, the paragraph subsequently refers to “the second fin 1523” and “the first fin 1522” when describing the active regions and their respective widths.
It is unclear whether the references to the first fin 1522 and the second fin 1523 are intended to refer to structures of the second cell scheme 1510 shown in FIG. 15B, or whether different fins are intended.
Applicant is required to amend the specification to clarify the identities of the referenced fins and to provide consistent reference numerals.
The specification is objected to because paragraph [0089] contains an apparent inconsistency concerning the dimensions of the L-shaped active regions 301. Paragraph [0089] states that the active regions may have a first fin width Wf1 of about 40 nm and a second fin width Wf2 of about 10 nm, while further stating that “the width of the fins” decreases by an interval of between about 72 nm and about 102 nm, such as about 90 nm.
It is unclear how a fin width decreasing from approximately 40 nm toward approximately 10 nm decreases by an interval of approximately 72 nm to 102 nm. Applicant is required to clarify the dimensional relationship and make any necessary correction.
Claim Objections
Claims 17 and 20 are objected to because of the following informalities:
Regarding claim 17, the recitation “wherein in the L-shaped active region has a third width and a fourth width” is grammatically incorrect because the phrase contains the unnecessary word “in” and lacks a proper grammatical subject for “has.” It appears that Applicant intended to recite “wherein the L-shaped active region has a third width and a fourth width.”
Appropriate correction is required.
Regarding claim 20, the recitation “wherein the third width and the fourth width are in a range from 8 nm and 50 nm” is grammatically incorrect because the expression “from 8 nm and 50 nm” does not properly define a range. It appears that Applicant intended to recite that the third width and the fourth width are “in a range from 8 nm to 50 nm.”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1-2 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11,699,729 (“Pat-729”) in view of Lo et al. (US 20080135949; in the IDS on 11/25/25; “Lo”).
Regarding claim 1. Claim 1 of Pat-729 teaches a method comprising depositing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially over a semiconductor substrate; etching the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the semiconductor substrate to form a fin, wherein a top surface of the fin has an L-shape in a top-down view; etching the first semiconductor layer and the third semiconductor layer to form a first nanostructure from the second semiconductor layer; forming a gate dielectric layer around the first nanostructure; and forming a gate electrode around the gate dielectric layer.
Thus, Pat-729 teaches the semiconductor-layer deposition, etching of the semiconductor layers and substrate to form an L-shaped fin, selective removal of the first and third semiconductor layers to form a nanostructure from the second semiconductor layer, formation of a gate dielectric layer around the nanostructure, and formation of a gate electrode around the gate dielectric layer, as required by instant claim 1.
But Pat-729 does not expressly teach that the etching forms both a first fin and an adjacent second fin, wherein the first fin has a first complex shape including a first L-shaped active region, the second fin has a second complex shape including a second L-shaped active region, and the first complex shape is a mirror image of the second complex shape.
However, Lo teaches the additional patterned-fin layout considerations that would have rendered this difference obvious.
Specifically, Lo teaches alternately depositing semiconductor channel layers 104 and interchannel layers 106 to form a multilayer stacked semiconductor structure 108. In the illustrated embodiment, channel layer 104 is Si and interchannel layer 106 is Ge, with SiGe also contemplated. Thus, Lo confirms that a vertically stacked semiconductor structure containing alternating semiconductor layers can be patterned into a desired fin geometry.
Lo further teaches applying photoresist layer 110 over multilayer stacked structure 108, patterning the photoresist to define fin structure 112, and thereafter etching portions of multilayer stacked structure 108 not protected by the patterned mask to produce multilayer stacked fin structure 118. Thus, Lo teaches that the lateral or top-down configuration of a multilayer semiconductor fin is a design established through lithographic patterning followed by etching.
The resulting fin structure 118 includes a relatively narrow fin portion 114 connected between respective wider supporting portions 116. Lo further expressly teaches that fin portion 114 is not required to be centered between the supporting portions, but alternatively may be arranged toward either side thereof. As illustrated in FIGS. 1B-1D, the patterned geometry thereby provides oppositely oriented corner or L-shaped portions on opposing sides of the patterned semiconductor structure.
Significantly, Lo expressly teaches that its process is not limited to formation of a single multilayer stacked fin structure. Lo states that “a single multilayer stacked fin structure or a plurality of multilayer stacked fin structures” may be formed on the BOX layer and that the multilayer stacked fin structures may be arranged parallel to each other, horizontally on the support substrate, “or in any other desired manner.”
Therefore, Lo teaches that (1) the lateral geometry of a multilayer semiconductor fin can be selected through lithographic patterning and etching, (2) oppositely oriented L-shaped portions are known in such patterned semiconductor structures, and (3) a plurality of multilayer stacked fin structures may be formed and arranged relative to one another in a desired manner.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pat-729 by forming a plurality of the L-shaped fins taught by Pat-729 and arranging two adjacent L-shaped fins in opposite orientations, such that the complex shape including the L-shaped active region of one fin is the mirror image of the complex shape including the L-shaped active region of the adjacent fin.
One of ordinary skill in the art would have had reason to make such a modification because Lo teaches that multilayer semiconductor fin geometry and placement are controllable through conventional lithographic patterning and etching and expressly teaches forming a plurality of such fin structures in a desired relative arrangement. In view of Lo's teaching of oppositely oriented geometric portions and its express teaching that multiple patterned fins may be arranged as desired, arranging two of the L-shaped fins already taught by Pat-729 in opposite orientations would have been a predictable layout choice available to one of ordinary skill in the art.
In the proposed combination, Pat-729's L-shaped fin is not structurally redesigned. Rather, the known L-shaped fin of Pat-729 is repeated and the orientation of one of the adjacent fins is reversed relative to the other. Such an arrangement would predictably result in a first fin having a first complex shape including a first L-shaped active region and an adjacent second fin having a second complex shape including a second L-shaped active region, wherein the first and second complex shapes are mirror images of one another.
Moreover, the proposed modification would not alter the basic fabrication or operation taught by Pat-729. The first, second, and third semiconductor layers would continue to be deposited over the substrate and etched to form the fins; the first and third semiconductor layers would continue to be removed to form nanostructures from the second semiconductor layer; and the gate dielectric and gate electrode would continue to be formed around the resulting nanostructures. The modification concerns the number, relative placement, and orientation of the patterned L-shaped fins, rather than the underlying nanostructure-forming process.
Accordingly, the claimed arrangement represents no more than a predictable arrangement of the L-shaped semiconductor fin already claimed in Pat-729 using the known patterned-fin layout principles taught by Lo. Therefore, instant claim 1 is not patentably distinct from claim 1 of Pat-729 in view of Lo.
Regarding claim 2. Claim 4 of Pat-729 teaches forming a first source/drain region adjacent to a first side of an active region of the fin and forming a second source/drain region adjacent to a second side of the active region of the fin, wherein the first and second sides correspond to respective first and second widths of the active region. Claim 2 of Pat-729 teaches that the first and second widths are different and are measured along parallel directions.
Claim 5 of Pat-729 further expressly teaches that the first source/drain region has a third width and the second source/drain region has a fourth width, wherein the third width and the fourth width are different and are measured in parallel directions.
Thus, Pat-729 teaches first and second source/drain regions disposed at respective portions of the L-shaped active region and having different widths measured along parallel directions, as required by instant claim 2.
It would have been obvious to one of ordinary skill in the art, in implementing the adjacent mirror-image L-shaped fin arrangement discussed above with respect to instant claim 1, to retain the source/drain configuration expressly claimed in Pat-729, thereby providing first and second source/drain regions at respective ends of the first L-shaped active region and having different widths measured along parallel directions. Such a modification merely applies Pat-729's expressly claimed source/drain configuration to the first L-shaped fin of the plurality-of-fins arrangement suggested by Lo and would have produced the predictable claimed arrangement.
Regarding claim 16. Claim 15 of Pat-729 teaches a device comprising a vertical stack of nanostructures, a gate dielectric disposed around the nanostructures, a gate electrode around the gate dielectric, a first source/drain region adjacent the nanostructures and having a first width, and a second source/drain region adjacent the nanostructures and having a second width different from the first width, including the claimed dimensional relationship between the first and second source/drain regions.
Thus, Pat-729 claim 15 teaches the basic GAA device structure recited in instant claim 16, including the vertical stack of nanostructures, the surrounding gate dielectric and gate electrode, and the differently dimensioned source/drain regions adjacent the nanostructures. Instant claim 16 requires each nanostructure of the vertical stack to comprise an L-shaped active region when seen in a top-down view.
But Pat-729 claim 15 does not expressly teach that each nanostructure of the vertical stack comprises an L-shaped active region when seen in a top-down view.
However, Lo teaches the formation of stacked semiconductor nanostructures from a patterned multilayer semiconductor structure. In particular, Lo's FIGS. 1A–1D illustrate the process flow for forming the stacked silicon-germanium nanowire structure, and FIGS. 1B–1D illustrate the lateral patterned geometry of the multilayer semiconductor structure from which the nanostructures are formed. Lo further teaches patterning the multilayer stack by lithography and etching to define the lateral geometry of the multilayer fin structure. Accordingly, Lo demonstrates that the lateral shape of the stacked semiconductor layers, and consequently the nanostructures formed therefrom, may be defined through the patterned geometry of the multilayer semiconductor structure.
The geometry illustrated by Lo includes cornered portions having an L-shaped configuration when viewed from above, thereby suggesting the use of an L-shaped lateral geometry for the semiconductor nanostructures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the vertical stack of nanostructures of Pat-729 claim 15 using the L-shaped lateral geometry suggested by Lo. The motivation for doing so is that Lo teaches that the lateral geometry of stacked semiconductor nanostructures may be selected through lithographic patterning and etching of the multilayer semiconductor structure, thereby permitting the nanostructure geometry to be configured as desired while retaining the known stacked-nanostructure device architecture. Applying Lo's L-shaped/cornered geometry to the nanostructures of Pat-729 would therefore have been a predictable application of a known semiconductor patterning technique to a known vertical-stack nanostructure device.
Such a modification would not require changing the basic operating principle of Pat-729's device. Rather, it would merely modify the lateral/top-down geometry of the nanostructures while retaining Pat-729's vertical stack, gate dielectric, gate electrode, and source/drain regions. One of ordinary skill in the art would have had a reasonable expectation of success because Lo teaches forming the desired lateral geometry at the multilayer-patterning stage using conventional lithographic patterning and etching before formation of the stacked nanostructures.
The resulting device would comprise a vertical stack of nanostructures in which each nanostructure has the patterned L-shaped active-region geometry when seen in a top-down view, together with the gate dielectric, gate electrode, and differently dimensioned source/drain regions taught by Pat-729, thereby arriving at the subject matter of instant claim 16.
Claims 9-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11,699,729 (“Pat-729”)
Regarding claim 9. Claim 1 of Pat-729 teaches depositing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially over a semiconductor substrate; etching the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the semiconductor substrate to form a fin; etching the first semiconductor layer and the third semiconductor layer to form a first nanostructure from the second semiconductor layer; forming a gate dielectric layer around the first nanostructure; and forming a gate electrode around the gate dielectric layer.
The etching of the semiconductor layers and semiconductor substrate to form the fin, as taught by claim 1 of Pat-729, constitutes the claimed patterning of the semiconductor layers and semiconductor substrate into a fin.
Claims 2 and 3 of Pat-729 further teach the dimensional configuration of the fin. In particular, claim 2 teaches first and second widths of the fin measured along parallel directions, and claim 3 directly teaches the claimed relationship between the first and second widths.
Accordingly, claims 1–3 of Pat-729 teach or encompass each limitation of instant claim 9, including patterning the first, second, and third semiconductor layers and semiconductor substrate into a fin whose topmost surface has different first and second widths measured along parallel directions, followed by formation of the nanostructure from the second semiconductor layer and formation of the gate dielectric layer and gate electrode.
Regarding claim 10. Claim 4 of Pat-729 teaches forming a first source/drain region adjacent to a first side of the active region and forming a second source/drain region adjacent to a second side of the active region. Claim 5 of Pat-729 further teaches that the first source/drain region has a third width and the second source/drain region has a fourth width, wherein the third width and the fourth width are different. Thus, Pat-729 teaches first and second source/drain regions adjacent to the nanostructure and having different respective widths, as required by instant claim 10.
Pat-729 does not expressly recite epitaxially growing the first and second source/drain regions.
Nevertheless, it would have been obvious to one of ordinary skill in the art at the time of the invention to form the semiconductor source/drain regions of Pat-729 by epitaxial growth because epitaxial growth was a known technique for forming semiconductor source/drain regions adjacent to semiconductor channel structures. Employing epitaxial growth to form the source/drain regions already taught by Pat-729 would have constituted the use of a known fabrication technique for its known purpose and would have predictably resulted in semiconductor source/drain regions adjacent to the nanostructure.
One of ordinary skill in the art therefore would have found it obvious to epitaxially grow the first and second source/drain regions taught by Pat-729 while retaining their respective different widths, thereby arriving at the additional limitations of instant claim 10.
Therefore, instant claim 10 is not patentably distinct from claims 1–2 and 4–5 of Pat-729.
Allowable Subject Matter
Claims 1-20 would be allowable if overcome the nonstatutory double patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Yang (US 20090026543) teaches forming semiconductor fins having patterned geometries by etching a semiconductor layer. In particular, Yang describes an initial semiconductor substrate 8 comprising a handle substrate 10, buried insulator layer 20, and top semiconductor layer 30 (Figs. 3A–3B, [0071]). An insulator structure including first insulator layer 40 and second insulator layer 50 is subsequently formed over top semiconductor layer 30 (Figs. 4A–4B, [0074]).
Yang further teaches lithographically patterning the structure to form first and second recessed regions R1 and R2 having respective parallel edges E1 and E2 (Figs. 5A–5B, [0075]). Significantly, Yang states that recessed regions R1 and R2 may have a polygonal shape and/or include an elliptical portion, thereby demonstrating flexibility in defining the lateral geometry of the semiconductor pattern.
As illustrated in Figs. 6A–8B and described in [0079]–[0084], Yang applies a block copolymer layer 60, forms first and second parallel polymer block lines 61 and 62, and selectively removes the second polymeric block region 63, thereby producing an etch-mask pattern for defining the semiconductor fins.
Yang then expressly teaches, at [0085] and Figs. 9A–9B, transferring the pattern of the first and second parallel polymer block lines 61, 62 by reactive ion etching through first insulator layer 40 and into top semiconductor layer 30, thereby forming pluralities of first and second semiconductor fins 31, 32. Thus, Yang establishes that semiconductor fin geometries can be lithographically defined and transferred into a semiconductor layer by etching. Yang identifies Figs. 3A–10B as sequential fabrication views, with the “A” figures being top-down views and the corresponding “B” figures being vertical cross-sectional views.
However, Yang fails to teach or suggest a first fin having a first complex shape including a first L-shaped active region when seen in a top-down view and an adjacent second fin having a second complex shape including a second L-shaped active region wherein the first complex shape is a mirror image of the second complex shape, in combination with etching the first semiconductor layer and the third semiconductor layer in both the first fin and the second fin to form first nanostructures from the second semiconductor layer, as required by claim 1.
Accordingly, although Yang demonstrates known techniques for defining and etching semiconductor fin patterns—including polygonal patterning—Yang does not teach or suggest the particular claimed combination of adjacent mirror-image complex fins respectively including L-shaped active regions and selective removal of first and third semiconductor layers from both fins to form nanostructures from an intervening second semiconductor layer. Therefore, if the nonstatutory double patenting rejection is overcome, claim 1 would be allowable over the prior art of record.
Regarding claim 9, Yang (US 20090026543) teaches patterning semiconductor material to form semiconductor fins. In particular, Yang discloses an initial semiconductor substrate 8 comprising a handle substrate 10, a buried insulator layer 20, and a top semiconductor layer 30 (Figs. 3A–3B, [0071]). Yang subsequently forms first and second insulator layers 40, 50 over top semiconductor layer 30 (Figs. 4A–4B, [0074]).
As shown in Figs. 5A–5B and described in [0075], Yang lithographically patterns second insulator layer 50 to form first and second recessed regions R1, R2, having respective parallel edges E1, E2. Yang further teaches that recessed regions R1 and R2 may have a polygonal shape, demonstrating that the lateral geometry of the pattern may be selected during fabrication.
As shown in Figs. 6A–8B and described in [0079]–[0084], Yang forms block copolymer layer 60, first and second parallel polymer block lines 61, 62, and selectively removes second polymeric block region 63 to establish the pattern subsequently transferred into the semiconductor material.
In particular, Yang expressly teaches in [0085] and Figs. 9A–9B that the pattern formed by first and second parallel polymer block lines 61, 62 is transferred by reactive ion etching into first insulator layer 40 and top semiconductor layer 30 to form pluralities of first and second semiconductor fins 31, 32. Thus, Yang teaches forming patterned semiconductor fins by etching a semiconductor layer.
However, Yang fails to teach or suggest the claimed multilayer semiconductor stack comprising first, second, and third semiconductor layers sequentially deposited over the semiconductor substrate, wherein the first, second, and third semiconductor layers and the semiconductor substrate are patterned into a fin having a topmost surface with different first and second widths measured along parallel directions, followed by selectively etching the first and third semiconductor layers to form a nanostructure from the intervening second semiconductor layer.
Accordingly, although Yang teaches lithographic definition and etching of semiconductor material to form semiconductor fins having selected lateral geometries, Yang does not teach or suggest the particular multilayer fin structure and selective removal of the first and third semiconductor layers to release a nanostructure from the second semiconductor layer, in combination with the claimed different first and second widths of the topmost surface. Therefore, if the nonstatutory double patenting rejection is overcome, claim 9 would be allowable over the prior art of record.
Regarding claim 16, Yang (US 20090026543) teaches semiconductor FinFET structures comprising plural semiconductor fins. For example, Yang discloses first semiconductor fins 31 and second semiconductor fins 32 formed over buried insulator layer 20, with gate dielectric 70 disposed on middle portions of the fins and gate electrode 80 disposed on the gate dielectric (Figs. 1A–1B, [0063]). Yang further discloses source regions SR1, SR2 and drain regions DR1, DR2 disposed on opposite sides of gate electrode 80 [0064].
Yang also teaches fabrication of semiconductor fins from a semiconductor layer. In the process illustrated by Figs. 3A–10B, Yang begins with semiconductor substrate 8 comprising handle substrate 10, buried insulator layer 20, and top semiconductor layer 30 (Figs. 3A–3B, [0071]). Yang subsequently forms and patterns insulator layers 40, 50, including first and second recessed regions R1, R2 (Figs. 4A–5B, [0074]-[0075]). Yang expressly states that recessed regions R1 and R2 may have a polygonal shape.
As shown in Figs. 6A–9B and described in [0079]–[0085], Yang forms first and second parallel polymer block lines 61, 62, which are used as an etch pattern. In particular, [0085] teaches transferring the pattern by reactive ion etching through first insulator layer 40 and into top semiconductor layer 30 to form pluralities of first and second semiconductor fins 31, 32.
However, Yang fails to teach or suggest a vertical stack of nanostructures, wherein each nanostructure comprises an L-shaped active region when seen in a top-down view, with a gate dielectric layer disposed around each nanostructure and a gate electrode disposed around the gate dielectric layer, in combination with first and second source/drain regions adjacent the nanostructures and having the different widths recited in claim 16.
More particularly, Yang's semiconductor fins 31, 32 are formed by patterning and etching a top semiconductor layer 30. Yang does not disclose forming a vertical stack of released semiconductor nanostructures from a multilayer semiconductor stack, much less forming each nanostructure of such a vertical stack with the claimed L-shaped active region in top-down view. Yang's disclosure of polygonal recessed regions R1, R2 and patterned semiconductor fins therefore does not teach the particular stacked-nanostructure geometry and surrounding gate configuration required by claim 16.
Accordingly, although Yang demonstrates that semiconductor fin geometry may be defined through lithographic patterning and etching, Yang does not teach or suggest the particular combination of a vertical stack of nanostructures each having an L-shaped active region, the claimed gate-all-around configuration, and the claimed differently dimensioned source/drain regions. Therefore, if the nonstatutory double patenting rejection is overcome, claim 16 would be allowable over the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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