Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Field-Effect Transistor Having Dielectric-Isolated Source/Drain Regions and Method of Forming the Same.”
Specification
The specification is objected to because of the following informalities:
• Paragraph [0008] recites “a perspective view another example FinFET device.” The word “of” appears to be missing. Applicant is required to amend the phrase to read “a perspective view of another example FinFET device.”
• Paragraph [0011] recites “end portions of the fin are removed are removed.” The phrase “are removed” is duplicated. Applicant is required to delete the duplicated wording.
• Paragraph [0012] recites “when dimensions of the transistor becomes smaller.” Applicant is required to amend “becomes” to “become.”
• Paragraph [0012] recites “the transistor, made the currently disclosed method.” The word “by” appears to be missing. Applicant is required to amend the phrase to read “the transistor, made by the currently disclosed method.”
• Paragraph [0012] recites “relative to how much the sidewalls of the fin is exposed.” Applicant is required to correct the grammatical inconsistency, for example, to read “relative to how much of the sidewalls of the fin are exposed.”
• Paragraph [0023] recites “the upper portion of the fin 212 … protrude from between neighboring STI regions 400.” Applicant is required to amend “protrude” to “protrudes.”
• Paragraph [0036] recites “epitaxiallly.” Applicant is required to amend “epitaxiallly” to “epitaxially.”
• Paragraph [0036] recites “having the top surface of the dielectric structure 800 to have a v-shape (e.g., a convex).” The phrase is grammatically and technically unclear because a V-shaped surface is not clearly identified as convex or concave. Applicant is required to clarify the intended surface profile and correct the sentence accordingly.
• Paragraph [0037] recites “may be optimized tuned.” Applicant is required to delete either “optimized” or “tuned” to correct the duplicated grammatical construction.
• Paragraph [0038] recites “with one of the dielectric structures 800 vertically spaced it apart from the fin 212.” Applicant is required to correct the grammatical error, for example, to read “with one of the dielectric structures 800 vertically spacing the source/drain region apart from the fin 212.”
• Paragraphs [0040] and [0041] recite “phosphorous” when referring to the chemical element used as a dopant. Applicant is required to amend “phosphorous” to “phosphorus.”
• Paragraph [0041] recites “N-type impurities, such as phosphorous or arsenide.” “Arsenide” identifies a compound or anion rather than the elemental dopant apparently intended. Applicant is required to clarify the intended impurity and, if arsenic is intended, amend “arsenide” to “arsenic.”
• Paragraph [0047] recites “The central portions of the fin 212A is overlaid.” Applicant is required to correct the disagreement in number, for example, to read “The central portion of the fin 212A is overlaid.”
• Paragraph [0047] identifies reference numeral 1102 as the gate dielectric layer and reference numeral 1104 as the conductive gate electrode, but subsequently recites “The high-k dielectric layer 1104 may be formed.” Applicant is required to amend “1104” to “1102” in that sentence.
• Paragraph [0052] recites “a method of fabricating a semiconductor is device.” Applicant is required to delete the word “is” so that the phrase reads “a method of fabricating a semiconductor device.”
Appropriate correction of the foregoing informalities is required. Any amendment must comply with 35 U.S.C. § 112(a) and must not introduce new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11, 14 and 17-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, Claim 1 recites, in pertinent part, “a semiconductor fin of a transistor gate extending along a first axis between a first source/drain region and a second source/drain region.” It is unclear whether the semiconductor fin forms part of the transistor gate, belongs to a transistor having a gate, or is merely associated with the transistor gate.
The specification does not resolve this ambiguity. Rather, the specification describes semiconductor fin 212A as providing the transistor’s conduction channel and separately describes gate structure 1100, including gate dielectric layer 1102 and conductive gate electrode 1104, as extending over the semiconductor fin. See paragraphs [0024] and [0046]–[0047]. Thus, the specification treats the semiconductor fin and transistor gate as distinct structures.
The rejection may be overcome by amending claim 1 to separately recite the semiconductor fin and transistor gate. For example, claim 1 could be amended to recite:
“a semiconductor fin of a transistor, the semiconductor fin extending along a first axis between a first source/drain region and a second source/drain region; and
a transistor gate extending over the semiconductor fin, the transistor gate comprising a gate dielectric coupled to the semiconductor fin,"
Any amendment must comply with 35 U.S.C. § 112(a) and must not introduce new matter.
Further regarding claim 1, Claim 1 is further rejected under 35 U.S.C. § 112(b) as indefinite because the phrase “the dielectric structures” lacks clear antecedent basis. Claim 1 previously recites “a respective first dielectric structure and second dielectric structure” but subsequently refers collectively to “the dielectric structures.” It is unclear whether “the dielectric structures” refers exclusively to the previously recited first and second dielectric structures or to additional, unrecited dielectric structures. Furthermore, the phrase “a respective first dielectric structure and second dielectric structure” does not clearly establish the correspondence between the first and second source/drain regions and the first and second dielectric structures. Accordingly, the scope of claim 1 is unclear.
The Examiner recommends amending the limitation as follows to overcome the rejection:
“wherein a lower surface of the first source/drain region is disposed above a first dielectric structure, and a lower surface of the second source/drain region is disposed above a second dielectric structure, the first and second dielectric structures extending below a lower surface of the gate dielectric.”
Regarding claim 3, the claim inconsistently identifies a portion of the first source/drain region as “a first, central, portion,” “the first portion,” and “the first central portion.” It is unclear whether these expressions identify a single portion that is both the first portion and the central portion or identify separate first and central portions. Consequently, it is also unclear which portion has the recited first and second ends. Accordingly, the scope of the claimed first source/drain region is unclear.
For purposes of examination, the examiner interprets “a first, central, portion” as “a first central portion” and interprets the subsequent references to “the first portion” and “the first central portion” as referring to that same first central portion. This interpretation is made solely to facilitate examination and does not resolve the indefiniteness identified above.
The examiner recommends amending the limitation as follows to overcome the rejection:
“a first central portion disposed over the first dielectric structure;
a second portion disposed on a first end of the first central portion, along a second axis perpendicular to the first axis, the second portion disposed over a first spacer; and
a third portion disposed on a second end of the first central portion, opposite from the second portion along the second axis, the third portion disposed over a second spacer.”
Regarding claim 7, Claim 6, from which claim 7 depends, recites that “the first spacer and the first dielectric structure each comprise first sidewalls parallel to a third axis.” Thus, claim 6 introduces multiple “first sidewalls”—at least a first sidewall of the first spacer and a first sidewall of the first dielectric structure.
Claim 7 subsequently recites “the first sidewall” in the singular without identifying whether that sidewall is the first sidewall of the first spacer or the first sidewall of the first dielectric structure. Consequently, the limitation requiring “a distance from the first sidewall to the second sidewall” is subject to more than one reasonable interpretation. In particular, it is unclear whether the claimed distance is measured between two sidewalls of the first spacer or between a sidewall of the first dielectric structure and the second sidewall of the first spacer.
Accordingly, one of ordinary skill in the art would not be able to determine the boundaries of claim 7 with reasonable clarity.
The Examiner recommends clarifying that both sidewalls belong to the first spacer, if that is Applicant’s intent.
Regarding claims 2-11, because of their dependency on claim 1, these claims are also objected for the reasons set forth above with respect to claim 1.
Regarding claim 14, Claim 12, from which claim 14 depends, recites a single “source/drain region.” Claim 14 subsequently recites “a bottom surface of each of the source/drain region.” The phrase “each of” ordinarily refers to individual members of a plurality, whereas “the source/drain region” refers to the single source/drain region introduced in claim 12. Therefore, it is unclear whether claim 14 refers to the bottom surface of the single source/drain region recited in claim 12 or to respective bottom surfaces of multiple source/drain regions.
This ambiguity also makes it unclear how the height of the dielectric structure is measured. Accordingly, one of ordinary skill in the art would not be able to determine the metes and bounds of claim 14 with reasonable clarity.
The recommended amendment replaces “each of the source/drain region” with “the source/drain region,” thereby providing a clear antecedent relationship to the single source/drain region recited in claim 12.
Regarding claim 17, Claim 17 recites “removing a portion of the dielectric film to form a recess between each of the spacer pairs.” The phrase “a recess between each of the spacer pairs” does not clearly establish whether a single recess is formed among the plurality of spacer pairs or whether a respective recess is formed between the individual spacers of each spacer pair.
Claim 17 subsequently recites “first and second source/drain regions” that are both “disposed in the recess.” Because the preceding limitation does not clearly establish the number of recesses, it is unclear whether the first and second source/drain regions are disposed in a single common recess or in respective first and second recesses.
Claim 17 further recites that the source/drain regions extend “over an upper surface of a first and second of the spacer pairs defining the recess.” The phrase “a first and second of the spacer pairs” is grammatically and structurally ambiguous. It is unclear whether “first and second” identifies:
• a first spacer pair and a second spacer pair; or
• first and second individual spacers belonging to one spacer pair.
Moreover, the singular expression “an upper surface” does not clearly identify whether the claim requires a shared upper surface or respective upper surfaces of multiple spacers or spacer pairs. These ambiguities prevent one of ordinary skill in the art from determining the number and arrangement of the recesses, spacer pairs, and source/drain regions. Accordingly, the metes and bounds of claim 17 are unclear.
To overcome the rejection and clearly establish the respective correspondence among the spacer pairs, recesses, and source/drain regions, the Examiner recommends amending claim 17 as follows:
“17. A method of fabricating a semiconductor device, comprising:
forming a dielectric film over a plurality of spacer pairs elevated above an isolation region, the dielectric film extending below an upper surface of the isolation region;
removing portions of the dielectric film to form a first recess between individual spacers of a first spacer pair and a second recess between individual spacers of a second spacer pair; and
forming a first source/drain region over a first remaining portion of the dielectric film and forming a second source/drain region over a second remaining portion of the dielectric film, the first source/drain region being disposed in the first recess and extending over respective upper surfaces of the individual spacers of the first spacer pair, and the second source/drain region being disposed in the second recess and extending over respective upper surfaces of the individual spacers of the second spacer pair, the first and second source/drain regions being coupled to opposite ends of a semiconductor fin to form a transistor.”
The recommended amendment expressly identifies first and second spacer pairs and corresponding first and second recesses, and establishes which source/drain region is disposed in each recess. Any amendment must find support in the originally filed disclosure and must not introduce new matter.
Regarding claims 18, Claim 18 recites, in pertinent part, “wherein the trench is recessed from the top surface.” However, neither claim 18 nor claim 17, from which claim 18 depends, previously introduces “a top surface.” Claim 17 recites “an upper surface of the isolation region,” but it is unclear whether “the top surface” in claim 18 refers to that upper surface or to an unrecited top surface of another structure, such as the semiconductor fin, substrate, spacer layer, or dielectric film.
Because the identity of “the top surface” determines the reference from which the trench is recessed, the lack of clear antecedent basis creates uncertainty regarding the position and depth of the claimed trench. Accordingly, one of ordinary skill in the art would not be able to determine the metes and bounds of claim 18 with reasonable clarity.
To overcome the rejection and establish a clear antecedent relationship with the upper surface of the isolation region recited in claim 17, the Examiner recommends amending the relevant limitation of claim 18 as follows:
“removing at least one end portion of the semiconductor fin to form a trench comprising the recess and to expose an end of the semiconductor fin, wherein the trench is recessed below the upper surface of the isolation region.”
The recommended amendment replaces “the top surface” with “the upper surface of the isolation region,” thereby expressly identifying the reference surface from which the trench is recessed. Any amendment must find support in the originally filed disclosure and must not introduce new matter.
Regarding claims 18-20, because of their dependency on claim 17, these claims are also objected for the reasons set forth above with respect to claim 17.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1-2 and 8-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,136,657 (“Pat-657”). Although the claims at issue are not identical, they are not patentably distinct from each other:
Regarding claim 1. claim 1 of Pat-657 claims a semiconductor device comprising a semiconductor fin over a substrate and laterally extending along a first axis. Pat-657 further claims a first source/drain region extending from a first end of the semiconductor fin along the first axis and a second source/drain region extending from a second end of the semiconductor fin along the first axis. Consequently, the semiconductor fin of Pat-657 extends along the first axis between the first and second source/drain regions, as required by instant claim 1.
Claim 1 of Pat-657 also claims first and second dielectric structures associated with the respective first and second source/drain regions. In particular, Pat-657 claims that the first and second source/drain regions are vertically elevated by the first and second dielectric structures, respectively. Thus, the respective lower surfaces of the first and second source/drain regions are disposed above the corresponding first and second dielectric structures, as required by instant claim 1.
Claim 1 of Pat-657 further claims that each of the first and second dielectric structures extends vertically below a lower surface of a gate dielectric layer. Accordingly, Pat-657 claims the limitation of instant claim 1 requiring the dielectric structures to extend below a lower surface of a gate dielectric.
Claim 1 of Pat-657 therefore claims every reasonably ascertainable limitation of instant claim 1. Although Pat-657 additionally claims a substrate and more specifically defines the relationships among the semiconductor fin, source/drain regions, dielectric structures, and gate dielectric layer, those additional limitations merely render Pat-657 claim 1 narrower than instant claim 1. Pat-657 claim 1 defines a species falling entirely within the broader scope of instant claim 1.
A patented species anticipates a subsequently presented genus that encompasses the patented species because issuance of the later genus claim would extend the right to exclude already granted by the species claim. Therefore, instant claim 1 is not patentably distinct from claim 1 of Pat-657, and issuance of instant claim 1 would result in an unjustified extension of the patent right.
For purposes of this rejection, the phrase “a semiconductor fin of a transistor gate” in instant claim 1 is interpreted, to the extent reasonably possible, as identifying a semiconductor fin of a transistor associated with a gate. This interpretation is made solely to evaluate the claim for nonstatutory double patenting and does not withdraw or otherwise alter the separate rejection of claim 1 under 35 U.S.C. § 112(b).
Regarding claim 2. Claim 4 of Pat-657 depends from claim 1 and therefore incorporates all the limitations of Pat-657 claim 1 discussed above. Claim 4 of Pat-657 further claims that each of the first and second dielectric structures includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof.
This is the same material limitation recited in instant claim 2. Accordingly, claim 4 of Pat-657 claims all the limitations of instant claim 2. Therefore, instant claim 2 is not patentably distinct from claim 4 of Pat-657, and issuance of instant claim 2 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 8, claim 3 of Pat-657 depends from claim 1 and therefore incorporates all the limitations of Pat-657 claim 1 discussed above. Claim 3 of Pat-657 further claims that the first source/drain region and the second source/drain region are electrically isolated from the substrate by the first and second dielectric structures, respectively.
This is the same electrical-isolation limitation recited in instant claim 8. Accordingly, claim 3 of Pat-657 claims all the limitations of instant claim 8. Therefore, instant claim 8 is not patentably distinct from claim 3 of Pat-657, and issuance of instant claim 8 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 9, Claim 5 of Pat-657 depends from claim 1 and therefore incorporates all the limitations of Pat-657 claim 1 discussed above. Claim 5 of Pat-657 further claims that each of the first and second dielectric structures includes a high-k dielectric material.
This is the same high-k dielectric-material limitation recited in instant claim 9. Accordingly, claim 5 of Pat-657 claims all the limitations of instant claim 9. Therefore, instant claim 9 is not patentably distinct from claim 5 of Pat-657, and issuance of instant claim 9 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 10, Claim 8 of Pat-657 depends from claim 1 and therefore incorporates all the limitations of Pat-657 claim 1 discussed above. Claim 8 of Pat-657 further claims that the first and second dielectric structures have a height extending from the surface of the substrate to respective bottom surfaces of the first and second source/drain regions, the height ranging from about 1 nanometer (nm) to 100 nm.
This is the same dielectric-structure height and dimensional-range limitation recited in instant claim 10. Accordingly, claim 8 of Pat-657 claims all the limitations of instant claim 10. Therefore, instant claim 10 is not patentably distinct from claim 8 of Pat-657, and issuance of instant claim 10 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 11, Claim 9 of Pat-657 depends from claim 1 and therefore incorporates all the limitations of Pat-657 claim 1 discussed above. Claim 9 of Pat-657 further claims that each of the first and second source/drain regions has a width extending along the first axis that is equal to or greater than a width of the respective first and second dielectric structures extending along the first axis.
This is the same relative-width limitation recited in instant claim 11. Accordingly, claim 9 of Pat-657 claims all the limitations of instant claim 11. Therefore, instant claim 11 is not patentably distinct from claim 9 of Pat-657, and issuance of instant claim 11 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 12, Claim 11 of Pat-657 claims a semiconductor device comprising a conduction channel of a transistor disposed above a substrate, a source/drain region extending from an end of the conduction channel, and a dielectric structure extending from vertically below the conduction channel to vertically above the conduction channel. Claim 11 of Pat-657 further requires that the source/drain region is electrically isolated from the substrate by the dielectric structure.
These limitations correspond to all the limitations recited in instant claim 12. Although claim 11 of Pat-657 additionally requires the substrate to comprise a semiconductor material and the conduction channel and substrate to include semiconductor material, these additional limitations merely define a narrower species falling within the broader scope of instant claim 12.
Accordingly, claim 11 of Pat-657 claims every limitation of instant claim 12 and anticipates the broader genus presented by instant claim 12. Therefore, instant claim 12 is not patentably distinct from claim 11 of Pat-657, and issuance of instant claim 12 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 13, Claim 12 of Pat-657 depends from claim 11 and therefore incorporates all the limitations of Pat-657 claim 11 discussed above. Claim 12 of Pat-657 further claims that a bottom surface of the source/drain region is elevated vertically above a top surface of isolation regions by the dielectric structure, with the isolation regions disposed on respective sides of a lower portion of the conduction channel.
This is the same vertical-elevation and isolation-region arrangement recited in instant claim 13. Accordingly, claim 12 of Pat-657 claims all the limitations of instant claim 13. Therefore, instant claim 13 is not patentably distinct from claim 12 of Pat-657, and issuance of instant claim 13 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 14, Claim 13 of Pat-657 depends from claim 11 and therefore incorporates all the limitations of Pat-657 claim 11 discussed above. Claim 13 of Pat-657 further claims that the dielectric structure has a height extending from a surface recessed from a top surface of isolation regions to a bottom surface of the source/drain region, with the height ranging from about 1 nanometer (nm) to about 100 nm and the isolation regions disposed on respective sides of the lower portion of the conduction channel.
This is the same dielectric-structure height, dimensional range, recessed-surface relationship, and isolation-region arrangement recited in instant claim 14. Accordingly, claim 13 of Pat-657 claims all the reasonably ascertainable limitations of instant claim 14. Therefore, instant claim 14 is not patentably distinct from claim 13 of Pat-657, and issuance of instant claim 14 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 15, Claim 16 of Pat-657 depends from claim 11 and therefore incorporates all the limitations of Pat-657 claim 11 discussed above. Claim 16 of Pat-657 further claims that the conduction channel includes at least one fin-like structure protruding from the substrate.
This is the same fin-like conduction-channel limitation recited in instant claim 15. Accordingly, claim 16 of Pat-657 claims all the limitations of instant claim 15. Therefore, instant claim 15 is not patentably distinct from claim 16 of Pat-657, and issuance of instant claim 15 would result in an unjustified extension of the right to exclude granted by Pat-657.
Regarding claim 16, Claim 17 of Pat-657 depends from claim 11 and therefore incorporates all the limitations of Pat-657 claim 11 discussed above. Claim 17 of Pat-657 further claims that the conduction channel includes one or more sheet-like structures vertically spaced apart from the substrate, with each of the sheet-like structures being vertically spaced apart from each other by a gate structure.
This is the same sheet-like conduction-channel limitation recited in instant claim 16. Accordingly, claim 17 of Pat-657 claims all the limitations of instant claim 16. Therefore, instant claim 16 is not patentably distinct from claim 17 of Pat-657, and issuance of instant claim 16 would result in an unjustified extension of the right to exclude granted by Pat-657.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 9947804; “Frougier”).
Regarding claim 1. Frougier discloses a semiconductor device comprising a semiconductor fin formed from semiconductor substrate 102. The fin structure comprises transistor site 128 and nanosheet stack 114 disposed thereon. Frougier explains that transistor site 128 is formed from substrate 102, is structurally continuous with substrate 102, and may protrude from its upper surface (Fig. 25; col. 7, ll. 41–58). Frougier further expressly states that each fin includes a nanosheet stack 114 containing semiconductor nanosheets 116 (col. 15, ll. 1–7).
As shown in Figures 24–25, the semiconductor fin extends along the lateral cross-gate direction between first and second source/drain epitaxial regions 150 positioned on opposite sides of gate structure 120. Frougier identifies its cross-sectional views as extending in the “cross-gate direction” (col. 6, ll. 4–8), thereby teaching the recited first axis.
Gate structure 120 constitutes the transistor gate and includes work-function metal 166. Frougier expressly discloses a silicon-dioxide layer or other gate-dielectric material vertically separating the gate region from underlying nanosheet stack 114 and further discloses replacing upper semiconductor region 122 with a gate dielectric and/or conductive material (col. 15, ll. 20–29). Accordingly, Frougier teaches a gate dielectric coupled to the semiconductor fin.
Figures 24–25 further show respective first and second insulative regions 146 beneath the first and second source/drain epitaxial regions 150. Frougier states that regions 146 are positioned directly beneath source/drain epitaxial regions 150 and that the source/drain regions are disposed above and in contact with insulative regions 146 (col. 17, ll. 54–56 and 64–65 through col. 18, ll. 1–2). As shown in Figure 25, the insulative regions 146 extend downward to substrate 102 and below the lower surface of the gate dielectric associated with gate structure 120 and nanosheet stack 114.
Regarding claim 2. Frougier discloses the semiconductor device of claim 1 as discussed above and further discloses that insulative regions 146 are formed in pairs adjacent to respective transistor sites 128 (col. 10, ll. 50–58). Frougier further expressly discloses forming insulative regions 146 by anisotropic high-density-plasma deposition of an insulating material, such as silicon dioxide (SiO₂) (col. 11, ll. 5–9). Accordingly, the respective first and second dielectric structures 146 comprise silicon oxide, as recited in claim 2.
Regarding claim 3. Frougier discloses the semiconductor device of claim 1 as discussed above. Frougier further discloses source/drain epitaxial region 150 epitaxially formed from exposed sidewalls of semiconductor nanosheets 116 of nanosheet stack 114, and inner spacers 148 positioned laterally adjacent to sacrificial nanosheets 118 and vertically between semiconductor nanosheets 116 (Fig. 24; col. 11, ll. 22–35; col. 17, ll. 40–67).
For purposes of examination, and without withdrawing the rejection of claim 3 under 35 U.S.C. § 112(b), the Examiner interprets “a first, central, portion,” “the first portion,” and “the first central portion” as referring to the same first central portion.
Under this interpretation, Frougier discloses that the first source/drain region comprises:
a first central portion disposed over the first dielectric structure, wherein the claimed first central portion corresponds to the portion of source/drain epitaxial region 150 facing and laterally adjacent to the middle semiconductor nanosheet 116 of nanosheet stack 114 and disposed over insulative region 146;
a second portion disposed on a first end of the first central portion along a second axis perpendicular to the first axis, the second portion disposed over a first spacer, wherein the claimed second portion corresponds to the lower portion of source/drain epitaxial region 150 disposed at a first vertical end of the first central portion relative to the middle semiconductor nanosheet 116. The second axis extends vertically and is perpendicular to the first axis. As shown in Figure 24, the lower portion of source/drain epitaxial region 150 extends laterally over the lower inner spacer 148, which corresponds to the claimed first spacer; and
a third portion disposed on a second end of the first central portion, opposite from the second portion along the second axis, the third portion disposed over a second spacer, wherein the claimed third portion corresponds to the upper portion of source/drain epitaxial region 150 disposed at an opposite second vertical end of the first central portion relative to the middle semiconductor nanosheet 116. As shown in Figure 24, the upper portion of source/drain epitaxial region 150 extends laterally over the upper inner spacer 148, which corresponds to the claimed second spacer.
Although Frougier does not separately label the first central, second, and third portions, the claim does not require those portions to be physically separate or formed from different materials. Rather, the claimed portions constitute identifiable subregions of the continuous source/drain epitaxial region 150 based on their respective spatial relationships to the middle semiconductor nanosheet 116, insulative region 146, and the lower and upper inner spacers 148. Those relationships are expressly illustrated in Figure 24.
Regarding claim 8. Frougier discloses the semiconductor device of claim 1 as discussed above, Frougier further discloses that insulative regions 146 are formed by depositing an electrically insulating material, such as silicon dioxide, and that an upper surface of each insulative region 146 extends above substrate 102 (col. 11, lines 5–20). Frougier also discloses that source/drain epitaxial regions 150 are formed above substrate 102 and in contact with insulative regions 146 in short-channel region 100S (col. 17, lines 40–67 through col. 18, line 2).
As clearly shown in Figures 24 and 25, a respective insulative region 146 is continuously interposed between each source/drain epitaxial region 150 and substrate 102. Because each region 146 is formed of an electrically insulating material and physically separates the corresponding source/drain epitaxial region 150 from substrate 102, each region 146 necessarily prevents direct electrical conduction between the corresponding source/drain epitaxial region 150 and substrate 102. Accordingly, the first and second source/drain epitaxial regions 150 are electrically isolated from substrate 102 by the respective first and second insulative regions 146.
The presence of any additional insulating material, such as insulative liner 144, does not alter this disclosure because insulative regions 146 remain electrically insulating structures directly interposed between the respective source/drain epitaxial regions 150 and substrate 102 and therefore contribute to and provide the claimed electrical isolation.
Regarding claim 11. Frougier discloses the semiconductor device of claim 1 as set forth above. Frougier further discloses first and second source/drain epitaxial regions 150 and corresponding first and second insulative regions 146 extending laterally along the direction of the nanosheet fin, corresponding to the claimed first axis (Fig. 15).
As shown in Figure 15, the lateral boundaries of each insulative region 146 are disposed within the lateral footprint of the corresponding source/drain epitaxial region 150. Accordingly, each source/drain epitaxial region 150 has a width extending along the first axis that is equal to or greater than the width of its corresponding insulative region 146 extending along the same axis. Frougier therefore discloses each of the first and second source/drain regions having a width along the first axis that is equal to or greater than the width of the corresponding first and second dielectric structures, as claimed (Fig. 15; see also Figs. 24–25).
Claims 12 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bi et al. (US 20190305106; “Bi”).
Regarding claim 12. Bi discloses a semiconductor device comprising nanosheet transistor 140 formed over substrate 102 (Fig. 1; ¶ [0032]).
Bi discloses a conduction channel comprising vertically stacked semiconductor nanosheet channel regions 122A, 124A, and 126A of nanosheet transistor 140 (Fig. 1; ¶¶ [0050] and [0057]).
Bi further discloses source/drain region 1310 extending from respective ends of the conduction channel. In particular, source/drain region 1310 is epitaxially grown from the exposed end sidewalls of nanosheet channel regions 122A, 124A, and 126A and is electrically coupled to the channel regions (Fig. 1; ¶¶ [0053]-[0054] and [0057]).
Bi further discloses a dielectric structure comprising interlayer dielectric region 1302. Interlayer dielectric region 1302 comprises an oxide dielectric material and is formed over substrate 102 (¶ [0055]). As shown in Figure 1, interlayer dielectric region 1302 extends vertically from the upper surface of substrate 102, at a level below the lowest nanosheet channel region 122A, to a level above the highest nanosheet channel region 126A. Thus, interlayer dielectric region 1302 extends from vertically below the conduction channel to vertically above the conduction channel.
Figure 1 further shows interlayer dielectric region 1302 disposed between the bottommost portion of source/drain region 1310 and substrate 102. Because region 1302 is a dielectric material that physically separates source/drain region 1310 from substrate 102, source/drain region 1310 is electrically isolated from substrate 102 by dielectric structure 1302.
Regarding claim 15, Bi discloses the semiconductor device of claim 12 as set forth above. Bi further discloses fin-shaped columns 202A protruding vertically from semiconductor substrate 102 (Fig. 9; ¶ [0043]). Each fin-shaped column 202A includes semiconductor channel layers 122A, 124A, and 126A arranged in an alternating vertical stack with sacrificial semiconductor layers 112B, 114B, 116B, and 118B (Figs. 9–11; ¶¶ [0043] and [0050]).
Bi further discloses selectively removing the sacrificial semiconductor layers while retaining semiconductor channel layers 122A, 124A, and 126A, thereby forming the nanosheet conduction channel of transistor 140 from the semiconductor portions of fin-shaped column 202A (Fig. 1; ¶¶ [0056]–[0057]). The resulting gate structure 1404, 1406 surrounds the retained semiconductor channel layers and regulates current flow through those layers between source/drain regions 1310 and 1312 (Fig. 1; ¶ [0057]).
Accordingly, Bi expressly identifies the channel-forming semiconductor structure as fin-shaped column 202A protruding from substrate 102 and discloses forming the conduction channel from the semiconductor channel portions of that fin-shaped structure. Bi therefore discloses a conduction channel including at least one fin-like structure protruding from the substrate, as recited in claim 15.
Regarding claim 16, Bi discloses the semiconductor device of claim 12 as set forth above. Bi further discloses that the conduction channel comprises vertically stacked semiconductor nanosheet channel regions 122A, 124A, and 126A (Fig. 1; ¶¶ [0050] and [0057]). As shown in Figure 1, semiconductor nanosheet channel regions 122A, 124A, and 126A are vertically spaced above substrate 102 and are vertically spaced apart from one another.
Bi further discloses a gate structure comprising gate dielectric layer 1402, work-function metal region 1404, and metal gate structure 1406 surrounding the stacked semiconductor nanosheet channel regions 122A, 124A, and 126A (Fig. 1; ¶ [0057]). The gate structure extends within the vertical spaces between adjacent nanosheet channel regions such that each nanosheet channel region is vertically spaced from the adjacent nanosheet channel region by the intervening gate structure.
Accordingly, Bi discloses a conduction channel including one or more sheet-like structures vertically spaced apart from the substrate, each of the sheet-like structures being vertically spaced apart from the other sheet-like structures by a gate structure, as recited in claim 16.
Claims 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 10573755; “Frougier”).
Regarding claim 17, Frougier discloses a method of fabricating a semiconductor device, namely a nanosheet field-effect transistor having buried-oxide isolation between its source/drain regions and substrate.
Frougier discloses forming semiconductor nanosheet fins 210, as shown in Figure 5. Each nanosheet fin 210 comprises alternating semiconductor Si sheets 201 and SiGe layers 205. Frougier expressly identifies structures 210 as “nanosheet fins.” The claimed “semiconductor fin” is not limited to a single-layer or unitary fin and does not exclude a multilayer nanosheet fin. Accordingly, Frougier’s semiconductor nanosheet fin 210 satisfies the claimed semiconductor fin.
Frougier further discloses forming inner spacers 920 in divots located at opposite ends of the semiconductor layers of nanosheet fins 210, as shown in Figure 9. The inner spacers at the respective ends of the vertically arranged semiconductor layers constitute a plurality of spacer pairs.
Frougier thereafter discloses forming dielectric film 1910 over and around the plurality of spacer pairs 920, as shown in Figures 19 and 20. Specifically, Frougier deposits SiO₂ dielectric film 1910 using a flowable chemical-vapor-deposition oxide-fill process. Dielectric film 1910 fills the area within conformal liner 1710 and beneath nanosheet fins 210. As shown particularly in Figure 20, dielectric film 1910 extends below the upper surface of isolation region 335.
Frougier subsequently discloses removing a portion of dielectric film 1910 to form a recess between the spacer pairs, as shown in Figure 21. Frougier explains that SiO₂ dielectric film 1910 is isotropically recessed and conformal liner 1710 is isotropically etched. A portion of dielectric film 1910 remains beneath nanosheet fins 210 and provides buried-oxide isolation between the subsequently formed source/drain regions and substrate 230. See also Frougier claim 5, which expressly recites “forming a recess in the oxide fill between the nanosheet fins.”
Frougier further discloses epitaxially forming first and second source/drain regions 2310 over the remaining portion of dielectric film 1910, as shown in Figure 23. Source/drain regions 2310 occupy the recess and extend upward and laterally over the upper surfaces of the respective inner spacer pairs 920 defining the recess. The remaining portion of dielectric film 1910 is positioned beneath source/drain regions 2310 and electrically isolates those regions from substrate 230.
The first and second source/drain regions 2310 are coupled to opposite ends of each semiconductor nanosheet fin 210, thereby forming a transistor. Frougier claim 6 expressly confirms this relationship by reciting epitaxial growth of a source region on one side of each nanosheet fin and a drain region on the opposite side of each nanosheet fin, in and above the recess.
Regarding claim 18, Frougier discloses the method of claim 17 and further discloses forming a dummy gate structure straddling a central portion of semiconductor nanosheet fin 210, as shown in Figure 3. The dummy gate structure includes amorphous silicon 325 formed over oxide layer 330 and capped by silicon-nitride layer 320 and silicon-oxide layer 315. Conformal spacer 310 is formed along the sidewalls of the dummy gate structure. Thus, Frougier discloses a dummy gate structure extending over and straddling a central portion of semiconductor nanosheet fin 210.
Frougier further discloses removing end portions of semiconductor nanosheet fin 210 to form source/drain trenches and expose respective ends of the nanosheet fin, as shown in Figure 5. Frougier explains that a reactive-ion-etch process removes portions of spacer material 310 and that an overetch removes portions of nanosheet fin 210 and sacrificial silicon layer 220. This etching produces a source/drain trench adjacent to the remaining central portion of nanosheet fin 210 and recessed below the upper surface of isolation region 335.
Frougier subsequently deposits dielectric film 1910 in the source/drain trench, as shown in Figures 19 and 20, and removes a portion of dielectric film 1910 to form the dielectric-film recess shown in Figure 21. Accordingly, the source/drain trench initially formed by removal of the end portions of nanosheet fin 210 comprises the subsequently formed recess in dielectric film 1910.
Frougier additionally discloses replacing the dummy gate structure with active gate structure 2740, as shown in Figure 27. Specifically, Frougier removes the dummy gate structure, including amorphous silicon 325 and oxide layer 330, removes sacrificial SiGe layers 205 to release semiconductor Si sheets 201, and forms active gate structure 2740 around the released Si sheets. Active gate structure 2740 includes high-k metal-gate material 2730, conductive gate fill 2720, and gate cap 2710.
Thus, Frougier discloses forming a dummy gate structure straddling a central portion of semiconductor fin 210, removing at least one end portion of the semiconductor fin to form a trench comprising the dielectric-film recess and expose an end of the semiconductor fin, and replacing the dummy gate structure with active gate structure 2740.
Regarding claim 19, Frougier discloses the method of claim 18 and further discloses forming a spacer layer over the dummy gate structure. Specifically, Frougier deposits conformal SiN liner 910 over nanosheet fins 210 and the dummy gate structures, with the liner material filling divots at opposite ends of the semiconductor layers to form inner spacers 920, as shown in Figure 9. Frougier’s claim 1 likewise expressly recites depositing a first liner to fill the divots and conformally cover the nanosheet fins and dummy gate structures.
Frougier subsequently removes surface portions of spacer layer 910 to expose sacrificial silicon layer 220 beneath nanosheet fins 210, as shown in Figures 11 and 12. Frougier then removes exposed sacrificial silicon layer 220, thereby forming a trench between nanosheet fins 210 and underlying SiGe layer 225, as shown in Figures 13 and 14. Frougier thereafter removes the remaining exposed portions of SiN liner 910 while retaining the portions protected within the divots as inner spacers 920, as shown in Figures 9 and 15.
Accordingly, removal of portions of spacer layer 910 permits the underlying sacrificial silicon layer 220 to be removed and results in formation of the trench beneath semiconductor nanosheet fins 210. The portions of the spacer-layer material retained in the divots constitute the plurality of inner-spacer pairs 920 previously identified with respect to claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 9 are rejected under 35 U.S.C. § 103 as being unpatentable over Frougier et al. (US 9947804; “Frougier”) in view of Song et al. (US 20180190829; “Song”).
Regarding claim 4. Frougier discloses the semiconductor device of claim 3 as discussed above. But Frougier does not expressly disclose that the first spacer extends along the third axis both: below an upper surface of the first dielectric structure; and above a lower surface of the first source/drain region.
However, Song discloses the missing spacer arrangement in an analogous nanosheet transistor. Song discloses protruding portions 104 and nanowires 120 extending along an X-axis, gate electrode 130 extending along a Y-axis, and a vertical Z-axis perpendicular to the X- and Y-axes (Figs. 1 and 20; ¶¶[0022] and [0027]). Under the axis nomenclature of claim 4, Song’s X-, Z-, and Y-axes correspond respectively to the claimed first, second, and third axes.
Song further discloses third spacers 142 positioned between vertically adjacent nanowires 120 and between the lowermost nanowire 120 and substrate 101. Song expressly identifies third spacer 142 as an “inner spacer” and identifies the lowermost third spacer 142 as a “lowermost inner spacer” defining a lateral boundary of void 108 beneath source/drain region 105 (¶¶[0029]–[0031]). The claimed first spacer corresponds to Song’s lowermost inner spacer 142.
Song expressly states that the Figure 20 embodiment combines the structures of the preceding embodiments and includes source/drain region 105, third spacer 142, and underlying insulating layer 143 in the same device (Fig. 20; ¶¶[0099]–[0103]). As shown in Figure 20, lowermost inner spacer 142 extends along the Y-axis, perpendicular to the longitudinal X-axis and the vertical Z-axis.
Song also discloses the claimed vertical relationships. Lowermost inner spacer 142 is positioned between the lowermost nanowire 120 and substrate 101 (¶[0029]), while the upper end of insulating layer 143 extends higher than the upper surface of the lowermost nanowire 120 (¶[0102]). Thus, at least a lower portion of lowermost inner spacer 142 necessarily extends below the upper surface of insulating layer 143, which corresponds to the claimed first dielectric structure.
Song further discloses that at least a portion of the lower surface of source/drain region 105 is positioned lower than the lower surface of the lowermost nanowire 120 (¶¶[0034]–[0035]). Because lowermost inner spacer 142 is positioned adjacent to and below the lowermost nanowire 120, Figure 20 shows that an upper portion of lowermost inner spacer 142 extends above the lower surface of source/drain region 105, which corresponds to the claimed first source/drain region.
Accordingly, Song discloses lowermost inner spacer 142 extending along the transverse Y-axis such that the spacer extends both below an upper surface of insulating layer 143 and above a lower surface of source/drain region 105 (Fig. 20; ¶¶[0029]–[0035] and [0099]–[0104]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dimensions and position of Frougier’s lowermost inner spacer 148 in accordance with Song, such that inner spacer 148 extends along the transverse third axis, below the upper surface of insulative region 146 and above the lower surface of source/drain epitaxial region 150.
A person of ordinary skill would have been motivated to make this modification because Song teaches that the lowermost inner spacer defines and laterally seals the isolation region beneath the source/drain region (¶¶[0030]–[0031] and [0103]–[0105]). Song expressly teaches that providing the isolation region beneath the source/drain region improves the punch-through characteristics of the semiconductor device (¶[0112]).
Song additionally teaches forming third spacer 142 and insulating layer 143 from a deposited insulating material during the same fabrication sequence (¶¶[0097], [0102], and [0110]). Song explains that its fabrication arrangement simplifies the semiconductor-manufacturing process and reduces process costs (¶[0113]). Song therefore provides express reasons to apply its overlapping spacer and underlying-insulation arrangement to an analogous nanosheet transistor.
Both references concern nanosheet transistors having vertically stacked semiconductor channels, dielectric inner spacers positioned between the channels, epitaxially formed source/drain regions, and electrical isolation beneath the source/drain regions. The proposed modification would therefore involve applying a known spacer arrangement to Frougier’s analogous device according to its established function. It would not change Frougier’s principle of operation, and a person of ordinary skill would have had a reasonable expectation of successfully obtaining the predictable benefits of improved isolation, improved punch-through characteristics, and simplified fabrication.
The resulting modified Frougier device would include a lowermost inner spacer 148 extending along the third axis below an upper surface of insulative region 146 and above a lower surface of source/drain epitaxial region 150, thereby satisfying every limitation of claim 4.
Regarding claim 5, Frougier discloses the semiconductor device of claim 3 as discussed above. But Frougier does not expressly disclose wherein: the first spacer extends along the third axis above an isolation region; and the isolation region extends along the third axis below the first dielectric structure.
However, Song discloses the missing spacer-and-isolation arrangement in an analogous nanosheet semiconductor device.
Song identifies element 103 as an isolation insulating layer and discloses that isolation insulating layer 103 is disposed on substrate 101 and covers side surfaces of protruding portions 104, which are also identified as active fins (¶¶[0025]–[0026]). Song further discloses a Figure 20–21 embodiment that includes source/drain region 105, spacer 141″, insulating layer 143, isolation insulating layer 103, and protruding portions 104 in the same semiconductor device 100B (¶¶[0099]–[0102]).
The claimed first dielectric structure corresponds to Song’s insulating layer 143, and Song’s spacer 141″ supplies the claimed positional relationship of the first spacer. As shown in Figure 21 and described in paragraph [0102]:
spacer 141″ is disposed on isolation insulating layer 103 and therefore extends along the Y-axis above isolation insulating layer 103; and
insulating layer 143 is disposed on protruding portions 104 and spacer 141″, while isolation insulating layer 103 extends along the Y-axis underneath insulating layer 143.
Figure 21 is a Y-Z cross-sectional view in which the Y-axis extends horizontally and the Z-axis extends vertically. Under the axis nomenclature of claim 5, the Y-axis corresponds to the claimed third axis. Thus, Figure 21 discloses spacer 141″ extending along the third axis above isolation insulating layer 103 and isolation insulating layer 103 extending along the third axis below insulating layer 143.
Song further discloses that isolation insulating layer 103, spacer 141″, and insulating layer 143 form part of the dielectric arrangement beneath source/drain region 105. In particular, Song discloses void 109 between isolation insulating layer 103 and source/drain region 105, with the void bounded by source/drain region 105, spacer 141″, and insulating layer 143 (¶¶[0103]–[0108]). Song therefore teaches using the claimed relative arrangement to provide a dielectric boundary between the source/drain region and the underlying substrate and active-fin structures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Frougier’s device by arranging its first inner spacer 148 and first insulative region 146 over an isolation region in accordance with the known arrangement taught by Song, such that first spacer 148 extends along the transverse third axis above the isolation region and the isolation region extends along the third axis below first insulative region 146.
A person of ordinary skill would have been motivated to make this modification to provide additional electrical isolation beneath and laterally adjacent to the source/drain region and to separate neighboring active-fin structures. Song expressly teaches using isolation insulating layer 103, spacer 141″, and insulating layer 143 to define the dielectric boundary beneath source/drain region 105 (¶¶[0102]–[0108]). Song further teaches that providing isolation beneath the source/drain region improves the punch-through characteristics of the semiconductor device (¶[0112]).
Song also teaches that its arrangement can simplify the semiconductor-manufacturing process and reduce process costs (¶[0113]). A person of ordinary skill therefore would have had express reasons to incorporate Song’s spacer-and-isolation arrangement into Frougier’s nanosheet device.
Both Frougier and Song disclose nanosheet transistors having stacked semiconductor channel structures, dielectric spacers, epitaxial source/drain regions, and dielectric structures positioned beneath the source/drain regions. Applying Song’s known spacer-and-isolation arrangement to Frougier would have involved the predictable use of known semiconductor isolation structures according to their established functions. The modification would not change Frougier’s principle of operation, and a person of ordinary skill would have had a reasonable expectation of success.
The resulting modified Frougier device would include first spacer 148 extending along the third axis above an isolation region, with the isolation region extending along the third axis below first insulative region 146, thereby satisfying every limitation of claim 5.
Regarding claim 6, Frougier discloses the semiconductor device of claim 3 as discussed above. But Frougier does not expressly disclose that the first spacer and the first dielectric structure each comprise a first sidewall parallel to a third axis perpendicular to the first and second axes.
However, Song discloses a semiconductor device having an inner spacer 142 corresponding to the claimed first spacer and an insulating layer 143 corresponding to the claimed first dielectric structure (Figs. 1 and 20; ¶¶ [0029], [0099]–[0104]). Figure 1 establishes that the semiconductor channel extends along the X-axis and that the gate extends along the Y-axis, while the Z-axis is the vertical direction. Accordingly, the Y-axis is perpendicular to both the X-axis and the Z-axis and corresponds to the claimed third axis.
As shown in Figure 20, insulating layer 143 includes a first sidewall on its right side, and the lowermost inner spacer 142 includes a first sidewall on its left side. Because Figure 20 is an X-Z cross-sectional view taken along line I-I′ of Figure 1, the respective sidewall surfaces extend into the plane of Figure 20 along the Y-axis. Thus, the first sidewall of insulating layer 143 and the first sidewall of inner spacer 142 are each parallel to the third axis, which is perpendicular to the first and second axes.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first spacer and first dielectric structure of Frougier with the transverse sidewall orientation taught by Song. Such an arrangement would provide defined lateral boundaries for the dielectric-isolation region beneath the source/drain region and thereby facilitate electrical isolation and improved punch-through characteristics, as taught by Song (¶¶ [0103]–[0105] and [0112]). Because Frougier and Song both concern stacked-channel semiconductor devices having inner spacers and dielectric structures beneath source/drain regions, the modification would have involved the predictable use of a known structural arrangement in a similar device, with a reasonable expectation of success.
Regarding claim 7, Frougier in view of Song discloses the semiconductor device of claim 6 as set forth above.
For purposes of prior-art examination, and without withdrawing the rejection under 35 U.S.C. § 112(b), Examiner interprets “the first sidewall” as referring to a first sidewall of the first spacer and “the second sidewall” as referring to an opposed sidewall of the first spacer, such that the distance between the first and second sidewalls defines a local thickness of the first spacer.
Frougier discloses inner spacer 148 corresponding to the claimed first spacer. Frougier, however, does not expressly disclose that the distance between the opposed sidewalls of inner spacer 148 is at a maximum proximal to an isolation region and at a minimum distal from the isolation region.
Song discloses inner spacer 142 disposed between lowermost nanowire 120 and substrate 101 adjacent isolation insulating layer 103 (Figs. 20–21; ¶¶ [0025]–[0031] and [0101]–[0104]). As shown in Figure 20, inner spacer 142 includes opposed bounding sidewalls. Song further expressly discloses that one side surface of inner spacer 142 may have a convex shape toward gate electrode 130, thereby providing a nonuniform distance between the opposed spacer sidewalls (¶ [0029]).
Song additionally teaches that the geometry of spacer 142 is controlled through deposition and etching. In particular, Song forms side spaces by laterally etching sacrificial patterns 160, expressly discloses controlling the depth and concavity of the resulting side surfaces, deposits an insulating material into the side spaces, and subsequently etches the deposited insulating material to form inner spacer 142 (¶¶ [0064]–[0069]). Song further teaches nonconformally depositing the insulating material such that the material is deposited more thickly on an upper surface of substrate 101 than on a side surface of nanowire 120, followed by etching the material to form inner spacer 142 and insulating layer 143 (¶¶ [0097] and [0110]).
Because isolation insulating layer 103 is disposed on substrate 101 and adjacent the lower portion of the semiconductor structure, Song’s preferentially thicker deposition near substrate 101 provides an express process bias toward forming a greater spacer thickness proximal to isolation insulating layer 103 and a smaller spacer thickness farther from isolation insulating layer 103. Thus, Song recognizes both the spacer profile and the deposition and etching conditions controlling that profile as adjustable structural and process variables.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure Frougier’s inner spacer 148 according to Song’s convex, nonconformally deposited spacer profile, including controlling the deposition and subsequent etching so that the distance between the opposed spacer sidewalls is greatest proximal to the isolation region and smallest distal from the isolation region. Song provides an express reason for this configuration: lowermost inner spacer 142 defines a side boundary of and assists in sealing void 108 beneath source/drain region 105 (¶¶ [0030]–[0031]). Providing greater spacer thickness near the isolation region would predictably provide sufficient dielectric material at the lower boundary of the void, while decreasing the spacer thickness farther from the isolation region would preserve space adjacent the semiconductor channel and source/drain region. Song further teaches that the resulting isolated void beneath the source/drain region improves punch-through characteristics (¶ [0112]).
The proposed modification would have required only routine adjustment of Song’s expressly disclosed deposition thickness, side-etch depth, and spacer etch conditions. A person of ordinary skill would have reasonably expected the modification to succeed because Song forms the disclosed spacer profile using conventional deposition and etching operations and expressly teaches controlling those operations to obtain the desired spacer dimensions. Moreover, claim 7 does not require a particular taper angle, dimensional ratio, or degree of thickness variation beyond the relative maximum and minimum. Accordingly, the claimed profile represents no more than a predictable optimization of the spacer geometry expressly taught by Song.
Therefore, Frougier in view of Song renders the subject matter of claim 7 obvious.
Regarding claim 9, Frougier discloses the semiconductor device of claim 1 as discussed above. But Frougier does not expressly disclose that each of the first and second insulative regions 146 includes a high-k dielectric material.
However, Song discloses insulating layer 143 disposed beneath source/drain region 105 and above substrate 101 (Figs. 20–21; ¶¶ [0101]–[0104]). Song further discloses that insulating layer 143 may be formed of the same material as inner spacer 142 (¶ [0102]). Song expressly identifies silicon nitride as one of the dielectric materials from which spacer 142 may be formed (¶ [0069]). Accordingly, Song teaches an embodiment in which insulating layer 143 comprises silicon nitride.
The instant specification explains that a high-k dielectric material may have a dielectric constant greater than about 4.0, or even greater than about 7.0 (instant specification, ¶ [0031]). Claim 9 does not limit the high-k material to a particular metal oxide, silicate, composition, or specific dielectric-constant value. Examiner interprets “high-k dielectric material,” under the broadest reasonable interpretation consistent with the specification, as encompassing a dielectric material having a dielectric constant greater than that of silicon dioxide, including a material having a k value greater than about 4.0.
Silicon nitride has an inherent dielectric constant of approximately 7, which is greater than the dielectric constant of silicon dioxide and greater than the approximately 4.0 threshold identified in the instant specification. Therefore, Song’s disclosed silicon-nitride insulating layer 143 constitutes a high-k dielectric material within the broadest reasonable interpretation of claim 9. The fact that Song does not expressly label silicon nitride as “high-k” is not controlling because the claimed property is an inherent physical property of the expressly disclosed material.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form each of Frougier’s first and second insulative regions 146 from Song’s disclosed silicon-nitride material. Frougier expressly permits insulative regions 146 to comprise electrically insulating materials other than silicon dioxide, and Song identifies silicon nitride as a suitable dielectric material for insulating layer 143 positioned beneath a source/drain region in a similar stacked-channel semiconductor device. Thus, the references themselves establish that silicon dioxide and silicon nitride were known dielectric-material options for structures performing the same electrical-isolation function.
Substituting Song’s silicon nitride for Frougier’s silicon dioxide would have amounted to the substitution of one known dielectric material for another known dielectric material to obtain the predictable result of an electrically insulating structure having a dielectric constant greater than that of silicon dioxide. A person of ordinary skill would have been motivated to make the substitution to provide a desired dielectric constant and to obtain material and process compatibility with adjacent spacer structures. Song additionally teaches forming inner spacer 142 and insulating layer 143 from the same deposited insulating material (¶¶ [0097], [0102], and [0110]), thereby simplifying the fabrication process and reducing process costs (¶ [0113]).
A person of ordinary skill would have reasonably expected the substitution to succeed because both Frougier and Song use the identified materials as dielectric structures in nanosheet semiconductor devices, and Song expressly demonstrates the formation of a silicon-nitride dielectric structure in the relevant source/drain-isolation environment. Applying Song’s material teaching to both corresponding insulative regions 146 of Frougier would result in each of the first and second dielectric structures including a high-k dielectric material, as required by claim 9.
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over Frougier et al. (US 9947804; “Frougier”) in view of Reznicek et al. (US 20190109052; in the IDS on 7/29/24; “Reznicek”).
Regarding claim 10, Frougier discloses the semiconductor device of claim 1 as discussed above. But Frougier does not expressly disclose that the height of each insulative region 146 ranges from about 1 nm to about 100 nm.
However, Reznicek discloses a semiconductor nitride layer 24 formed on the exposed surface of semiconductor substrate 10 and serving as a substrate-isolation dielectric layer in a nanosheet semiconductor device (Figs. 7–9; ¶¶ [0050]–[0052] and [0068]). Reznicek expressly discloses that semiconductor nitride layer 24 may comprise silicon nitride and has a thickness from 2 nm to 6 nm (¶ [0051]). Reznicek further teaches that layer 24 prevents bottom-up epitaxial growth of source/drain regions 26 and assists in eliminating an undesired leakage path and parasitic transistor formation beneath the nanosheet device (¶¶ [0045], [0051]–[0052], and [0067]–[0068]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the height of each of Frougier’s insulative regions 146 according to Reznicek’s disclosed substrate-isolation dielectric thickness of 2 nm to 6 nm. Both Frougier and Reznicek concern nanosheet semiconductor devices employing dielectric material over a semiconductor substrate to electrically isolate the source/drain region and suppress undesirable conduction or epitaxial growth through the substrate. Reznicek therefore provides an express teaching of a suitable nanoscale dimension for a dielectric substrate-isolation structure performing the same or substantially similar function as Frougier’s insulative region 146.
Applying Reznicek’s disclosed 2 nm to 6 nm dimension to each of Frougier’s insulative regions 146 would have amounted to the predictable use of a known substrate-isolation dielectric dimension in a similar nanosheet device. A person of ordinary skill would have reasonably expected the modification to succeed because Reznicek expressly employs that thickness to provide substrate isolation and prevent bottom-up source/drain growth. In the resulting modified Frougier device, each insulative region 146 would extend from the surface of substrate 102 to the lower surface of the corresponding source/drain epitaxial region 150 and would have a height between 2 nm and 6 nm.
Reznicek’s entire disclosed range of 2 nm to 6 nm lies within the claimed range of about 1 nm to about 100 nm. The instant specification does not disclose that the claimed range, or either endpoint of the range, is critical to the operation or performance of the semiconductor device. The instant specification also does not disclose any unexpected result attributable to selecting a dielectric-structure height within the claimed range instead of a height known in the prior art. Further, no evidence of unexpected results associated with the claimed range is presently of record.
Accordingly, selecting a height within the claimed range would have constituted no more than the predictable selection and optimization of a known dielectric-isolation dimension. Applying Reznicek’s expressly disclosed 2 nm to 6 nm thickness to Frougier’s first and second insulative regions 146 results in each dielectric structure having a height, extending from the surface of substrate 102 to the bottom surface of the corresponding source/drain epitaxial region 150, within the claimed range of about 1 nm to about 100 nm.
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Bi et al. (US 20190305106; “Bi”) in view of Song et al. (US 20180190829; “Song”).
Regarding claim 13, Bi discloses the semiconductor device of claim 12 as set forth above. But Bi does not explicitly disclose isolation regions disposed on respective sides of a lower portion of the conduction channel, with a bottom surface of the source/drain region elevated vertically above upper surfaces of the isolation regions by the dielectric structure.
However, Song discloses a nanosheet semiconductor device comprising source/drain region 105, insulating layer 143, isolation insulating regions 103, protruding portion 104, and nanosheet channel regions 120 (Fig. 21; ¶¶ [0101]-[0103]). As shown in Figure 21, the bottom surface of source/drain region 105 is vertically elevated above the upper surfaces of isolation insulating regions 103, and insulating layer 143 is disposed in the intervening region beneath source/drain region 105. Song further discloses that insulating layer 143 is disposed over protruding portion 104 and spacers 141″ and between substrate 101 and the region underlying source/drain region 105 (¶¶ [0102]-[0103] and [0107]-[0108]). Thus, insulating layer 143 provides a dielectric structure by which the bottom surface of source/drain region 105 is vertically elevated above the upper surfaces of isolation insulating regions 103.
Song further discloses isolation insulating regions 103 disposed on opposing lateral sides of protruding portion 104 (Fig. 21; ¶ [0102]). Protruding portion 104 forms the lower portion of fin structure FS supporting nanosheet channel regions 120 (¶¶ [0026]-[0027] and [0051]). Accordingly, isolation insulating regions 103 are disposed on respective sides of the lower portion of the channel-supporting fin structure, corresponding to the claimed isolation regions disposed on respective sides of a lower portion of the conduction channel.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s nanosheet transistor by providing Song’s isolation insulating regions 103 on respective sides of the lower channel-supporting portion and configuring the lower portion of Bi’s dielectric structure 1302 to include Song’s insulating-layer arrangement 143 beneath the source/drain region. Both Bi and Song concern nanosheet transistors having vertically stacked semiconductor channels and source/drain regions formed at the ends of those channels. Song’s arrangement therefore constitutes the application of a known nanosheet-device isolation arrangement to Bi’s similar nanosheet transistor, with the predictable result of electrically separating the source/drain region from the substrate and laterally isolating adjacent active regions, without changing the principle of operation of Bi’s transistor.
Claim 14 is rejected under 35 U.S.C. § 103 as being unpatentable over Bi et al. (US 20190305106; “Bi”) in view of Song et al. (US 20180190829; “Song”) and further in view of Reznicek et al. (US 20190109052; in the IDS on 7/29/24; “Reznicek”).
Regarding claim 14, Bi discloses the semiconductor device of claim 12 as set forth above. But Bi does not explicitly disclose that the dielectric structure has a height extending from a surface recessed from a top surface of isolation regions to a bottom surface of each source/drain region, wherein the height ranges from approximately 1 nm to approximately 100 nm and the isolation regions are disposed on respective sides of a lower portion of the conduction channel.
However, Song discloses isolation insulating regions 103 disposed on substrate 101 and on opposing sides of protruding portion 104, which forms the lower portion of fin structure FS supporting nanosheet channel regions 120 (Fig. 21; ¶¶ [0026]–[0027], [0051], and [0101]–[0102]). Song further discloses source/drain regions 105 elevated above isolation insulating regions 103 and insulating layer 143 disposed in the intervening region beneath source/drain regions 105 (Fig. 21; ¶¶ [0102]–[0103] and [0107]–[0108]). Thus, Song teaches the claimed isolation-region arrangement and a dielectric structure extending upwardly toward the bottom surface of the source/drain region from a surface below the upper surfaces of isolation insulating regions 103.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s nanosheet transistor to include Song’s isolation insulating regions 103 and underlying insulating-layer arrangement 143. Both Bi and Song concern nanosheet transistors having vertically stacked semiconductor channels and source/drain regions formed at the ends of those channels. Providing Song’s isolation arrangement in Bi would constitute the application of a known nanosheet isolation structure to a similar nanosheet device, with the predictable result of electrically isolating adjacent active regions and improving electrical separation between the source/drain region and the substrate.
But Bi and Song do not explicitly disclose the claimed height range.
However, Reznicek discloses a nanosheet transistor having semiconductor nitride dielectric isolation layer 24 formed on a surface of semiconductor substrate 10 beneath source/drain region 26 (Fig. 9; ¶¶ [0050]–[0052] and [0057]–[0058]). Reznicek expressly discloses that dielectric isolation layer 24 has a thickness of approximately 2 nm to approximately 6 nm (¶ [0051]), which falls entirely within the claimed range of approximately 1 nm to approximately 100 nm. Reznicek further discloses dielectric ILD material 30 beneath source/drain region 26 and in physical contact with dielectric isolation layer 24, thereby providing a dielectric structure extending from the substrate-facing surface to the bottom surface of source/drain region 26 (Fig. 9; ¶¶ [0057]–[0058] and [0068]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the dielectric structure of the Bi in view of Song’s device according to Reznicek’s dielectric-isolation arrangement and to select its height in accordance with Reznicek’s disclosed 2 nm to 6 nm range. Reznicek expressly teaches that dielectric isolation layer 24 prevents bottom-up epitaxial growth and eliminates parasitic transistor formation beneath the nanosheet device (Abstract; ¶¶ [0004], [0051], and [0067]–[0068]). Accordingly, a person of ordinary skill would have had reason to employ Reznicek’s disclosed dielectric dimension in the combined device to obtain the predictable benefits of source/drain-to-substrate isolation and suppression of parasitic transistor formation.
The claimed range is broad and encompasses Reznicek’s expressly disclosed range. Furthermore, the instant specification does not disclose that the claimed range is critical and does not identify any unexpected result attributable to selecting a dielectric-structure height within the claimed range. Accordingly, the combined teachings of Bi, Song, and Reznicek render claim 14 obvious.
Claim 20 is rejected under 35 U.S.C. § 103 as being unpatentable over Frougier et al. (US 10573755; “Frougier”) in view of Song et al. (US 20180190829; “Song”).
Regarding claim 20, Frougier discloses the method of claim 17 and further discloses that dielectric film 1910 comprises silicon dioxide, which is one of the dielectric materials expressly recited in claim 20.
Frougier further teaches a remaining dielectric-film height falling within the claimed range of about 1 nm to about 100 nm. Frougier discloses that sacrificial silicon layer 220 has a thickness of approximately 50–100 nm and that the sacrificial layer is removed and replaced by BOX dielectric 1910. Frougier additionally discloses that SiGe layer 225 may have a thickness of approximately 5 nm, while Frougier claim 12 recites that the thinnest portion of the oxide is approximately ten times the thickness of the SiGe layer. Thus, Frougier teaches a remaining oxide thickness of approximately 50 nm, which falls within the claimed range.
But Frougier does not expressly disclose that dielectric film 1910 includes a high-k dielectric material.
However, Song discloses insulating layer 143 positioned on isolation insulating layer 103 and below source/drain region 105′, as shown in Figure 17 and described in paragraph [0088]. Song teaches that insulating layer 143 may be formed of the same material as inner spacer 142. Paragraph [0069] of Song teaches that inner spacer 142 may comprise, among other materials, silicon nitride.
One of ordinary skill in the art would have recognized silicon nitride as a dielectric material having a dielectric constant greater than about 4 and, therefore, as a high-k dielectric under the standard provided by the instant specification. Silicon nitride is also expressly included in the group of dielectric materials recited in claim 20. Accordingly, Song teaches a material that satisfies both the claimed listed-material limitation and the claimed high-k limitation.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Song’s silicon-nitride dielectric material for at least a portion of Frougier’s dielectric film 1910. Both references employ dielectric materials in corresponding regions beneath or adjacent to source/drain structures to provide electrical isolation from an underlying substrate. Song expressly demonstrates that silicon nitride is suitable for an insulating structure positioned on an isolation region below a source/drain structure and that the same material may be used for adjacent inner spacers.
A skilled artisan therefore would have selected silicon nitride as a known dielectric alternative for Frougier’s buried dielectric structure to provide electrical isolation while maintaining material compatibility with the adjacent silicon-nitride spacer structures. Such a modification would have constituted the predictable use of a known dielectric material for its established insulating function, with a reasonable expectation of success.
Moreover, Frougier recognizes dielectric-isolation thickness as a result-effective variable. Frougier explains that a prior approximately 15-nm dielectric-isolation thickness provides a narrow downstream process margin and that its thicker BOX isolation improves source/drain isolation and prevents parasitic current. Thus, one of ordinary skill would have been motivated to select and optimize the height of the remaining dielectric film to obtain sufficient isolation and process margin.
The claimed range of about 1 nm to about 100 nm encompasses the approximately 50-nm thickness taught by Frougier. Furthermore, the instant specification does not identify the claimed range as critical, does not distinguish it from the thickness taught by Frougier, and does not disclose that the claimed range produces any unexpected result relative to Frougier’s disclosed thickness. Accordingly, the claimed range does not render claim 20 nonobvious.
Therefore, the combination of Frougier and Song teaches or suggests every limitation of claim 20, and claim 20 would have been obvious to one of ordinary skill in the art before the effective filing date.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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