Prosecution Insights
Last updated: October 01, 2026
Application No. 18/787,573

PASSIVATION LAYERS WITH ROUNDED CORNERS

Non-Final OA §102§103
Filed
Jul 29, 2024
Priority
Mar 09, 2022 — divisional of 12/322,646
Examiner
LINDSEY, COLE LEON
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
120 granted / 135 resolved
+28.9% vs TC avg
Moderate +13% lift
Without
With
+12.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
27 currently pending
Career history
163
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
14.9%
-25.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 135 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu (US20200395327A1). Regarding claim 1, Lu discloses a structure, comprising: a first insulating layer on a substrate (See below annotated fig. 4 dielectric layer 102 on die 101); a first conductive structure within the substrate (See below annotated fig. 4, par. 22 teaches that “[t]he semiconductor die 101 includes a conductive pad 103” and as pad 103 is part of die 101 it is also within it); a second conductive structure disposed on the first insulating layer and in contact with the first conductive structure (See below annotated fig. 4 conductive bumps 105 and 205 form a second conductive structure on dielectric layer 202 and in contact with conductive pad 103), wherein a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded (See below annotated fig. 4 the corner between second conductive structure and top surface of dielectric layer 102 is rounded); and a second insulating layer disposed on the first insulating layer and the second conductive structure (See below annotated fig. 4 dielectric layer 202 disposed on dielectric layer 102 and conductive structure 105 and 205). PNG media_image1.png 534 1011 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US20190305078A1, hereinafter Wu) in view of Lu (US20200395327A1). Regarding claim 1, Wu teaches a structure, comprising: a first insulating layer on a substrate (Fig. 1J dielectric layer 34 on structure 11); a first conductive structure within the substrate (Fig. 1J conductive layer 14 within structure 11); a second conductive structure disposed on the first insulating layer and in contact with the first conductive structure (Fig 1J conductive layer 37 disposed on dielectric layer 34); and a second insulating layer disposed on the first insulating layer and the second conductive structure (Fig. 1J passivation layer 40 disposed on contact 38a and dielectric layer 34). Wu does not appear to teach wherein a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded Lu teaches in fig. 4 and par. 25 that the “when a horizontal force is applied to the curved interface [between bump 105 and dielectric layer 102], such force would be dispersed” and so “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface.” Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu with the teachings of Lu such that a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded because “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface” (Lu par. 25). Regarding claim 2, the combination of Wu and Lu teaches the structure of claim 1, further comprising a metal-insulator-metal (MIM) structure within the first insulating layer (Wu fig. 1J MIM capacitor 100a). Regarding claim 3, the combination of Wu and Lu teaches the structure of claim 1, wherein the corner between the sidewall of the second conductive structure and the top surface of the first insulating layer is between about 95° and about 135° (Examiner notes par. 11 of the specification defines “about” as ±5% and so the claimed range is between 90.25° and 141.75°. Lu fig. 4 would reasonably suggest and disclose to a person of ordinary skill in the art the corner between bump 205 and dielectric layer 202 being between 90.25° and 141.75°). Regarding claim 4, the combination of Wu and Lu teaches the structure of claim 1, further comprising a barrier layer between the first insulating layer and the second conductive structure (Wu fig. 1J barrier layer 36 between conductive layer 37 and dielectric layer 34). Regarding claim 5, the combination of Wu and Lu teaches the structure of claim 1, wherein the second conductive structure comprises a copper redistribution layer (RDL) (Wu par. 41 teaches that “the materials of…the conductive layer 37…the same as or different from those of…conductive layer 14” and Wu par. 13 teaches that “[t]he conductive layer 14 includes, for instance, copper or other suitable metal”). Regarding claim 6, the combination of Wu and Lu teaches the structure of claim 1, wherein the second conductive structure comprises an aluminum redistribution layer (RDL) (Wu par. 41 teaches that “the materials of…the conductive layer 37…the same as or different from those of…conductive layer 14” and Wu par. 13 teaches that “[t]he conductive layer 14 includes, for instance, copper or other suitable metal.” As Wu also teaches the use of aluminum for conductive layer 19 in par. 16, they also teach wherein conductive layer 37 comprises aluminum). Regarding claim 7, the combination of Wu and Lu teaches the structure of claim 1, further comprising a third insulating layer disposed on the second insulating layer (Wu fig. 1J protection layer 41 disposed on passivation layer 40). Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wu (US20190305078A1) and Lu (US20200395327A1) as applied to claim 1 above, and further in view of Wu et al. (US10707179B1, hereinafter Wu’179). Regarding claim 8, the combination of Wu and Lu teaches the structure of claim 1. The combination of Wu and Lu does not appear to teach a polyimide layer on the second insulating layer; and a metal bump surrounded by the polyimide layer. Wu’179 teaches a polyimide layer on the second insulating layer (Wu’179 fig. polymer layer 246 and col. 9 teaches that “[t]he polymer layer 246 can include…polyimide (PI)”); and a metal bump surrounded by the polyimide layer (Wu’179 fig. 13 external connector 250 surrounded by polymer layer 246). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Wu and Lu with the teachings of Wu’179 because the combination of Wu’179’s polymer 246 and external connector 250 allows for a protected external connection and so a person of ordinary skill in the art would combine it the combination of Wu and Lu as taught in claim 1 and Wu fig. 1J in order to further protect the device. Regarding claim 9, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 8. Wu’179 further teaches an under bump metallization (UBM) layer in contact with a top surface of the second conductive structure and sidewalls of the polyimide layer (Wu’179 fig. 13 UBM 248 in contact with top surface of pad 232 and sidewalls of polymer layer 246); and a solder cap on the metal bump (Wu’179 col. 10 teaches that “[i]n some embodiments, the external conductor 250 can include a bump such as a Cu bump and a solder, though not shown”) Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Wu, Lu, and Wu’179 with further teachings from Wu’179 because, as Wu’179 teaches the external bump connection and polymer layer, they also teach the specific UBM and cap structure of the connection as well. Regarding claim 10, the combination of Wu and Lu teaches the structure of claim 1, further comprising: a third insulating layer disposed on the second insulating layer The combination of Wu and Lu does not appear to teach a polyimide layer disposed on the third insulating layer; and an under bump metallization (UBM) layer in contact with a top surface of the second conductive structure and sidewalls in contact with the second insulating layer, the third insulating layer, and the polyimide layer. Wu’179 teaches a polyimide layer disposed on the third insulating layer (Wu’179 fig. polymer layer 246 and col. 9 teaches that “[t]he polymer layer 246 can include…polyimide (PI)”); and an under bump metallization (UBM) layer in contact with a top surface of the second conductive structure and sidewalls in contact with the second insulating layer, the third insulating layer, and the polyimide layer (Wu’179 fig. 13 UBM 248 in contact with top surface of pad 232 and sidewalls of polymer layer 246). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Wu and Lu with the teachings of Wu’179 because the combination of Wu’179’s polymer 246 and UBM 248 allows for a protected external connection and so a person of ordinary skill in the art would combine it the combination of Wu and Lu as taught in claim 1 and Wu fig. 1J in order to further protect the device. Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US20190305078A1) in view of Lu (US20200395327A1) and Wu’179 (US10707179B1). Regarding claim 11, Wu teaches a structure, comprising: a dielectric layer disposed on a substrate (Fig. 1J dielectric layer 12 on substrate 10); a first conductive structure disposed within the dielectric layer (Fig. 1J conductive layer 14 within dielectric layer 12); a first insulating layer disposed on the dielectric layer and the first conductive structure (Fig. 1J dielectric structure 18); a second conductive structure on the first insulating layer and in contact with the first conductive structure through the first insulating layer (Fig. 1J conductive layer 37 on dielectric structure 18 and connects to conductive layer 14 through dielectric structure 18); a second insulating layer disposed on the first insulating layer and the second conductive structure (Fig. 1J dielectric layer 34 disposed on dielectric structure 18 and conductive layer 37). Wu does not appear to teach wherein a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded. a polyimide layer disposed on the second insulating layer; and a copper bump disposed on the second conductive structure and surrounded by the polyimide layer and the second insulating layer. Lu teaches in fig. 4 and par. 25 that the “when a horizontal force is applied to the curved interface [between bump 105 and dielectric layer 102], such force would be dispersed” and so “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface.” Wu’179 teaches a polyimide layer disposed on the second insulating layer (Wu’179 fig. polymer layer 246 and col. 9 teaches that “[t]he polymer layer 246 can include…polyimide (PI)”); and a copper bump disposed on the second conductive structure and surrounded by the polyimide layer and the second insulating layer (Wu’179 col. 10 teaches that “[i]n some embodiments, the external conductor 250 can include a bump such as a Cu bump and a solder, though not shown”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu with the teachings of Lu such that a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded because “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface” (Lu par. 25). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Wu and Lu with the teachings of Wu’179 because the combination of Wu’179’s polymer 246 and external connector 250 allows for a protected external connection and so a person of ordinary skill in the art would combine it the combination of Wu and Lu in order to further protect the device. Regarding claim 12, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 11, further comprising a metal-insulator-metal (MIM) structure within the first insulating layer (Wu fig. 1J MIM capacitor 100a). Regarding claim 13, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 11, further comprising: a barrier layer between the first insulating layer and the second conductive structure (Wu fig. 1J barrier layer 36 between conductive layer 37 and dielectric layer 34). Regarding claim 14, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 11, wherein the second conductive structure comprises a copper redistribution layer (RDL) or an aluminum RDL (Wu par. 41 teaches that “the materials of…the conductive layer 37…the same as or different from those of…conductive layer 14” and Wu par. 13 teaches that “[t]he conductive layer 14 includes, for instance, copper or other suitable metal”). Regarding claim 15, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 11, further comprising a third insulating layer disposed on the second insulating layer (Wu fig. 1J protection layer 41 disposed on passivation layer 40). Regarding claim 16, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 11, wherein the corner between the sidewall of the second conductive structure and the top surface of the first insulating layer is between about 95° and about 135° (Examiner notes par. 11 of the specification defines “about” as ±5% and so the claimed range is between 90.25° and 141.75°. Lu fig. 4 would reasonably suggest and disclose to a person of ordinary skill in the art the corner between bump 205 and dielectric layer 202 being between 90.25° and 141.75°). Regarding claim 17, Wu teaches a structure, comprising: a substrate comprising a top metallization (TME) layer (Fig. 1J conductive layer 14 within dielectric layer 12); a first insulating layer disposed on the substrate and TME layer (Fig. 1J dielectric structure 18); a conductive structure disposed on the first insulating layer and in contact with the TME layer through the first insulating layer (Fig. 1J conductive layer 37 on dielectric structure 18 and connects to conductive layer 14 through dielectric structure 18), a second insulating layer disposed on the first insulating layer and the conductive structure (Fig. 1J dielectric layer 34 disposed on dielectric structure 18 and conductive layer 37). Wu does not appear to teach wherein an angle between a sidewall of the conductive structure and a top surface of the first insulating layer is between about 95 ° and about 135 °, a polyimide layer disposed on the second insulating layer; and a metal bump disposed on the polyimide layer and the conductive structure. Lu teaches in fig. 4 and par. 25 that the “when a horizontal force is applied to the curved interface [between bump 105 and dielectric layer 102], such force would be dispersed” and so “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface.” Lu additionally teaches wherein an angle between a sidewall of the conductive structure and a top surface of the first insulating layer is between about 95 ° and about 135 ° (Examiner notes par. 11 of the specification defines “about” as ±5% and so the claimed range is between 90.25° and 141.75°. Lu fig. 4 would reasonably suggest and disclose to a person of ordinary skill in the art the corner between bump 205 and dielectric layer 202 being between 90.25° and 141.75°). Wu’179 teaches a polyimide layer disposed on the second insulating layer (Wu’179 fig. polymer layer 246 and col. 9 teaches that “[t]he polymer layer 246 can include…polyimide (PI)”); and a metal bump disposed on the polyimide layer and the conductive structure (Wu’179 col. 10 teaches that “[i]n some embodiments, the external conductor 250 can include a bump such as a Cu bump and a solder, though not shown”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu with the teachings of Lu such that a corner between a sidewall of the second conductive structure and a top surface of the first insulating layer is rounded because “the structure of curved interface could better prevent crack or delamination from occurring at the interface between the conductive bump 105 and the dielectric layer 102 compared to the vertical interface” (Lu par. 25). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Wu and Lu with the teachings of Wu’179 because the combination of Wu’179’s polymer 246 and external connector 250 allows for a protected external connection and so a person of ordinary skill in the art would combine it the combination of Wu and Lu in order to further protect the device. Regarding claim 18, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 17, further comprising a metal-insulator-metal (MIM) structure disposed within the first insulating layer (Wu fig. 1J MIM capacitor 100a). Regarding claim 19, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 17, wherein the metal bump is surrounded by the polyimide layer and the second insulating layer (Wu’179 fig. 13 polymer layer 246 surrounds external connector 250 and so the combination of Wu, Lu, and Wu’179 teaches wherein the bump as taught by Wu’179 is surrounded by polymer 246 as taught by Wu’179 and Wu’s dielectric layer 34 also surrounds the bump). Regarding claim 20, the combination of Wu, Lu, and Wu’179 teaches the structure of claim 17, wherein a ratio between a first thickness of a first portion of the first insulating layer and a second thickness of a second portion of the first insulating layer is between about 1.1 and about 2 (Examiner notes par. 11 of the specification defines “about” as ±5% and so the claimed range is a ratio between 1.045 and 2.1. Wu fig. 1J dielectric structure 18 has a tapered profile against contact 38a from a maximum thickness down to a thickness of 0. Therefore, there exist a first and second thicknesses of dielectric structure 18 along that tapered profile such that a ratio of the first thickness to the second thickness is between the ratio of 1.045 and 2.1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/Examiner, Art Unit 2812 /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 29, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+12.7%)
2y 10m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 135 resolved cases by this examiner. Grant probability derived from career allowance rate.

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