DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/20/2024 and 06/17/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “METHOD OF MAKING SEMICONDUCTOR ARRANGEMENT INCLUDING A SPACER USING ETCHING”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (U.S. PG Pub No US2020/0176552A1).
Regarding claim 17, Chang teaches a method [see figs. 11-22, 0070] of forming a semiconductor arrangement (trench capacitor [0070]), comprising:
forming a first conductive layer (second-from-uppermost 1304) fig. 13 [0075, 0077];
forming a first dielectric layer (uppermost 1302) fig. 13 [0075-0076] over the first conductive layer (second-from-uppermost 1304);
forming a first spacer (S1 portion of 1010 material acting as a spacer between 1020 and 112/114) fig. 21 [0091] (see annotated fig. 22 below) having a first (right) sidewall (directly) contacting a sidewall of the first conductive layer (second-from-uppermost 1304) and a sidewall of the first dielectric layer (uppermost 1302); and
forming a second dielectric layer (1020a) fig. 22 [0094], wherein the second dielectric layer (1020a) (thermally) contacts the first sidewall of the first spacer (S1) (thermally connected by proximity to connected 1010 material) and a second (left) sidewall of the first spacer (S1) on a diametrically opposite side of the first spacer (S1) relative to the first (right) sidewall (as defined in annotated fig. 22 below).
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Annotated fig. 22 of Chang
Regarding claim 18, Chang teaches the method [see figs. 11-22, 0070] of claim 17. Chang also teaches comprising:
forming a via portion (304c) fig. 22 [0094] of an interconnect structure (1006 comprising 304c) [0094] through the second dielectric layer (1020a) fig. 22 [0094] and the first dielectric layer (uppermost 1302) fig. 13 [0075-0076] to (directly) contact the first conductive layer (second-from-uppermost 1304) fig. 13 [0075, 0077].
Regarding claim 19, Chang teaches the method [see figs. 11-22, 0070] of claim 18. Chang also teaches wherein forming the via portion (304c) fig. 22 [0094] comprises forming the via portion (304c) such that the via portion (304c) is spaced apart from the first sidewall of the first spacer (S1 portion of 1010 material) [0091] (see annotated fig. 22 above) (diagonally spaced) by the second dielectric layer (1020a) fig. 22 [0094].
Regarding claim 20, Chang teaches the method [see figs. 11-22, 0070] of claim 17. Chang also teaches comprising:
forming a second conductive layer (uppermost 1304) fig. 13 [0075, 0077] over the first dielectric layer (uppermost 1302) fig. 13 [0075-0076]; and
forming a second spacer (S2 portion of 1010 material acting as a spacer between 1020 and 112/114) fig. 21 [0091] (see annotated fig. 22 below) (directly) contacting a (right) sidewall of the second conductive layer (uppermost 1304) (in fig. 21) prior to forming the second dielectric layer (1020a) fig. 22 [0094].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) in view of Hsu (U.S. PG Pub No US2016/0035817A1) and Ma (U.S. PG Pub No US2020/0044059A1).
Regarding claim 1, Chang teaches a method [see figs. 11-22, 0070] of forming a semiconductor arrangement (trench capacitor [0070]), comprising:
forming a first dielectric layer (uppermost 1302) fig. 13 [0075-0076];
forming a first conductive layer (uppermost 1304) fig. 13 [0075, 0077] over the first dielectric layer (uppermost 1302);
forming a first mask (1702) fig. 17 [0085] over a first portion (middle) of the first conductive layer (lower 1302); and
performing a first etch process [see fig. 17, 0085-0087] using the first mask (1702) as an etch template to remove a second portion (portions not covered by 1702) of the first conductive layer (uppermost 1304) and define a sidewall surface of the first conductive layer (sidewall of uppermost 1304 in fig. 17, after etching).
However, Chang does not explicitly disclose wherein:
performing the first etch process [see fig. 17, 0085-0087] comprises performing a phase of the first etch process [see fig. 17, 0085-0087] in the presence of a halogen precursor gas to form a first spacer over a portion of the sidewall surface of the first conductive layer (uppermost 1304) and cover an interface between the first conductive layer (uppermost 1304) and the first dielectric layer (uppermost 1302).
Hsu teaches a method [0029] wherein:
performing the first etch process [see figs. 3B-3C, 0032-0033] comprises performing a phase of the first etch process [see figs. 3B-3C, 0032-0033] in the presence of a gas (carrier gas / metal gas [0033]) to form a first spacer (lower 110C) fig. 3C [0033-0034] (acting as a sidewall spacer for 104) over (partially above) a portion of the sidewall surface of the first conductive layer (302/104) fig. 3C [0030-0031, 0033] and cover (conceal) an interface between the first conductive layer (104) and the first dielectric layer (102) fig. 3C [0030].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Chang to include the formation of protective sidewall spacers [0034, 0038] on the sidewalls of the capacitor electrode layer(s) [0030-0031] in order for the spacers to act as barriers that prevent metallic residue from damaging adjacent dielectric materials [0012, 0033], as taught by Hsu.
However, Chang in view of Hsu does not explicitly disclose performing a phase of the first etch process [see figs. 3B-3C, 0032-0033 Hsu] to form a first spacer (lower 110C) in the presence of a halogen precursor gas (Hsu does not explicitly disclose halogen gas [0033]).
Ma teaches a method [see fig. 7, 0056, 0064] comprising performing a phase of the first etch process [0063] to form (enable formation of) a first spacer (130) fig. 6 [0059] (liner acting as a sidewall spacer for 118 material [0059]) in the presence of a halogen precursor gas (precursor gas such as fluorine may be used to incorporate a non-metallic element into sidewall spacer 130 [0059, 0077]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the spacer formation method of Chang in view of Hsu such that the precursor gas(es) used to form the sidewall spacer(s) [0056, 0064] comprise a halogen element gas such as fluorine or chlorine [0077-0078] in order to incorporate a non-metallic element into the spacer material [0077-0078] and thereby selectively and favorably control charge properties of the spacer material [0021-0024, 0077-0078], as taught by Ma.
Regarding claim 2, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang in view of Hsu and Ma (with reference to Hsu) also teaches performing a process to remove [see fig. 3C, 0033-0034] the first mask (304) fig. 3B [0032] in the presence of the first spacer (110C) fig. 3C [0033-0034] (mask(s) 304 / 310 [0034] may be ‘left in place’ during passivation to form 110C, such that 110C is adjacent to mask 304 when initially formed [0034] – before mask removed).
Regarding claim 3, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang also teaches comprising:
forming a second dielectric layer (1602) fig. 16 [0085] (such as silicon nitride dielectric [0085, 0028]) over the first conductive layer (uppermost 1304) fig. 13 [0075, 0077] prior to forming the first mask (1702) fig. 17 [0085]; and
performing the first etch process [0086-0087] using the first mask (1702) as an etch template to remove a portion of the second dielectric layer (1602) and define a sidewall surface of the second dielectric layer (1602 sidewalls of fig. 17).
Further, Chang in view of Hsu and Ma (with reference to Hsu) wherein the first spacer (lower 110C) fig. 3D [0033-0034] covers (conceals) the (inner) sidewall surface of the second dielectric layer (106) fig. 3D [0035].
Regarding claim 4, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 3. Chang in view of Hsu and Ma (with reference to Hsu) also teaches first spacer (lower 110C) fig. 3D [0033-0034] covers (conceals from lateral perspective) an interface between the second dielectric layer (106) fig. 3D [0035] and the first conductive layer (104) fig. 3D [0030-0031, 0033].
Regarding claim 5, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang also teaches comprising:
forming a second conductive layer (second-from-uppermost 1304) fig. 13 [0075, 0077] over a second dielectric layer (second-from-uppermost 1302) fig. 13 [0075-0076], wherein forming the first dielectric layer (uppermost 1302) fig. 13 [0075-0076] comprises forming the first dielectric layer (uppermost 1302) over the second conductive layer (second-from-uppermost 1304);
forming a second mask (1802) fig. 18 [0088-0089] over a first portion of the first dielectric layer (uppermost 1302) and a first portion of the second conductive layer (second-from-uppermost 1304) after performing the first etch process [see fig. 17, 0087]; and
performing a second etch process [see fig. 18, 0088-0089] using the second mask (1802) as an etch template [see fig. 18, 0088-0089] to remove a second portion (portion not covered by 1802) of the first dielectric layer (uppermost 1302), to remove a second portion (portion not covered by 1802) of the second conductive layer (second-from-uppermost 1304) and define a sidewall surface of the second conductive layer (second-from-uppermost 1304), and to expose the second dielectric layer (second-from-uppermost 1302).
However, Chang does not explicitly disclose wherein:
performing the second etch process [see fig. 18, 0088-0089] comprises performing a phase of the second etch process [see fig. 18, 0088-0089] in the presence of a second halogen precursor gas to form a second spacer over a portion of the sidewall surface of the second conductive layer (second-from-uppermost 1304) and cover an interface between the second conductive layer (second-from-uppermost 1304) and the second dielectric layer (second-from-uppermost 1302).
Hsu teaches a method [0029] comprising performing the second etch process [see fig. 3F, 0037] comprises performing a phase of the second etch process [see fig. 3F, 0037] in the presence of a gas (carrier gas / metal gas [0033, 0037-0038]) to form (to enable formation of) a second spacer (upper 110C) fig. 3G [0038] (acting as a sidewall spacer for layer 108 [0038]) over (above) a portion of the sidewall surface of the second conductive layer (108) fig. 3G [0038] and cover (conceal) an interface between the second conductive layer (108) and the second dielectric layer (106) fig. 3G [0035].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Chang to include the formation of protective sidewall spacers [0034, 0038] on the sidewalls of the capacitor electrode layer(s) [0030-0031] in order for the spacers to act as barriers that prevent metallic residue from damaging adjacent dielectric materials [0012, 0033], as taught by Hsu.
However, Chang in view of Hsu does not explicitly disclose performing a phase of the second etch process [see figs. 3F-3G, 0037-0038 Hsu] to form a second spacer in the presence of a halogen precursor gas (Hsu does not explicitly disclose halogen gas [0033, 0038]).
Ma teaches a method [see fig. 7, 0056, 0064] comprising performing a phase of the second etch process [0063] to form (enable formation of) to form a second spacer (130) fig. 6 [0059] (liner acting as a sidewall spacer for 118 material [0059]) in the presence of a halogen precursor gas (precursor gas such as fluorine may be used to incorporate a non-metallic element into sidewall spacer 130 [0059, 0077]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the spacer formation method of Chang in view of Hsu such that the precursor gas(es) used to form the sidewall spacer(s) [0056, 0064] comprise a halogen element gas such as fluorine or chlorine [0077-0078] in order to incorporate a non-metallic element into the spacer material [0077-0078] and thereby selectively and favorably control charge properties of the spacer material [0021-0024, 0077-0078], as taught by Ma.
Regarding claim 6, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 5. Chang also teaches wherein:
performing the second etch process [see fig. 18, 0088-0089] using the second mask (1802) fig. 18 [0088-0089] as an etch template to remove the second portion of the first dielectric layer (uppermost 1302) fig. 17 [0075-0077] comprises removing the second portion (portion not covered by 1802) of the first dielectric layer (uppermost 1302) to define a sidewall surface (sidewalls after etching in fig. 18) of the first dielectric layer (uppermost 1302).
Further, Chang in view of Hsu and Ma (with reference to Hsu) wherein the second spacer (upper 110C) fig. 3G [0038] covers (conceals) the (inner) sidewall surface of the first dielectric layer (112) fig. 3I [0039-0040].
Regarding claim 7, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 5. Chang in view of Hsu and Ma (with reference to Hsu) also teaches comprising:
performing a process to remove the second mask (310) figs. 3F-3G [0037-0038] in the presence of the first spacer (lower 110C) fig. 3G [0034] and the second spacer (upper 110C) fig. 3G [0038] (mask(s) 304 / 310 [0034, 0037] may be ‘left in place’ during passivation to form 110C, such that upper and lower 110C coexist with mask 310 when upper 110C initially formed [0034, 0037] – before mask removed).
Regarding claim 8, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 5. Chang in view of Hsu and Ma (with reference to Hsu) also teaches wherein forming the second mask (310) figs. 3F-3G [0037-0038] comprises forming the second mask (310) over (above) the first spacer (lower 110C) fig. 3F [0034].
Regarding claim 9, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang in view of Hsu and Ma (with reference to Ma) also teaches wherein the first spacer (lower 110C) fig. 3F [0034] comprises a metal halide (may comprise aluminum chloride, for example [0077-0078 Ma]).
Regarding claim 10, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang also teaches wherein the first conductive layer (uppermost 1304) fig. 13 [0075, 0077]
comprises titanium nitride [0077].
Regarding claim 11, Chang in view of Hsu and Ma teaches the method [see figs. 11-22, 0070] of claim 1. Chang in view of Hsu and Ma (with reference to Ma) also teaches wherein the halogen precursor gas [0077-0078 Ma] comprises at least one of fluoride, chloride, or bromide [0077]
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) in view of Hsu (U.S. PG Pub No US2016/0035817A1).
Regarding claim 12, Chang teaches a method [see figs. 11-22, 0070] of forming a semiconductor arrangement (trench capacitor [0070]), comprising:
forming a first conductive layer (second-from-uppermost 1304) fig. 13 [0075, 0077];
forming a first dielectric layer (uppermost 1302) fig. 13 [0075-0076] over the first conductive layer (second-from-uppermost 1304);
forming a mask (1802) fig. 18 [0088-0089] over a first portion (portion of 1302 covered by 1802) of the first dielectric layer (uppermost 1302); and
performing an etch process [see fig. 18, 0088-0089] using the mask (1802) as an etch template to remove a second portion (portion of 1302 now covered by 1802) of the first dielectric layer (uppermost 1302) and a first portion (portion of 1304 not covered by 1802) of the first conductive layer (second-from-uppermost 1304).
However, Chang does not explicitly disclose performing an/the etch process to form a first spacer adjacent a second portion of the first conductive layer (second-from-uppermost 1304) and the first portion of the first dielectric layer (uppermost 1302).
Hsu teaches a method [0029] comprising performing an etch process [see fig. 3F, 0037] to form (to enable formation of) a first spacer (upper 110C) fig. 3G [0038] (acting as a sidewall spacer for layer 108 [0034]) adjacent a second (remaining) portion of the first conductive layer (108) fig. 3G [0038] and the first (remaining) portion of the first dielectric layer (112) fig. 3H [0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Chang to include the formation of protective sidewall spacers [0034, 0038] on the sidewalls of the capacitor electrode layer(s) [0030-0031] in order for the spacers to act as barriers that prevent metallic residue from damaging adjacent dielectric materials [0012, 0033], as taught by Hsu.
Regarding claim 13, Chang in view of Hsu teaches the method [see figs. 11-22, 0070] of claim 12. Chang in view of Hsu (with reference to Hsu) also teaches wherein performing the etch process [see fig. 3F, 0037] to form (to enable formation of) the first spacer (upper 110C) fig. 3C [0038] comprises performing the etch process [see fig. 3F, 0037] to form the first spacer (upper 110C) adjacent the mask (310) fig. 3F [0037] (mask(s) 304 / 310 [0034, 0037] may be ‘left in place’ during passivation to form 110C, such that 110C is adjacent to mask 310 when initially formed [0034, 0037] – before mask removed).
Regarding claim 14, Chang in view of Hsu teaches the method [see figs. 11-22, 0070] of claim 12. Chang in view of Hsu (with reference to Hsu) also teaches comprising:
performing a process to remove (photolithography to pattern [0037]) the mask (310) fig. 3F [0037] and expose (leave exposed/unprotected) a (top) surface of the first spacer (upper 110C) fig. 3C [0038] adjacent the mask (310) prior to the mask (310) being (fully) removed (mask(s) 304 / 310 [0034, 0037] may be ‘left in place’ during passivation to form 110C, such that 110C is adjacent to mask 310 when initially formed [0034, 0037] – before mask fully removed).
Regarding claim 15, Chang in view of Hsu teaches the method [see figs. 11-22, 0070] of claim 12. Chang also teaches wherein:
forming the first conductive layer (second-from-uppermost 1304) fig. 13 [0075, 0077] comprises forming the first conductive layer (second-from-uppermost 1304) on (supported by) a second dielectric layer (second-from-uppermost 1302) fig. 13 [0075, 0076]; and
performing the etch process [see fig. 18, 0088-0089] comprises performing the etch process to expose the (top of) second dielectric layer (second-from-uppermost 1302).
Regarding claim 16, Chang in view of Hsu teaches the method [see figs. 11-22, 0070] of claim 15. Chang in view of Hsu (with reference to Hsu) also teaches wherein the first spacer (108) fig. 3G [0038] covers an interface between the second dielectric layer (106) fig. 3G [0035-0036] and the first conductive layer (108) fig. 3G [0038].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature trench capacitors formed by progressive steps of masking and etching.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/05/2026
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