Prosecution Insights
Last updated: October 01, 2026
Application No. 18/787,608

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103§112
Filed
Jul 29, 2024
Priority
Mar 30, 2021 — provisional 63/167,939 +1 more
Examiner
LEE, WOO KYUNG
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
167 granted / 204 resolved
+21.9% vs TC avg
Moderate +13% lift
Without
With
+12.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
37 currently pending
Career history
226
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.7%
+11.7% vs TC avg
§102
20.5%
-19.5% vs TC avg
§112
27.7%
-12.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 204 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, in the limitation, “an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer” recited on lines 7-8, it is not clear what the term “density” refers to, because “density” may refer to a volume density or an areal density, and a mass density or a number density, and these measures may provide different, or even opposite, results for the oxidized upper portion and the unoxidized lower portion. Applicants originally disclosed that “the volume of the oxidized third seal layer 146 may be greater than the volume of the third seal layer 146, such as by up to about 10%” ([0047] of the present application), and oxidation typically incorporates oxygen into the silicon nitride layer, thereby changing both composition and mass of the upper portion. For example, the density of oxygen atoms may increase in the oxidized upper portion even if the layer expands in volume. Therefore, depending on whether “density” is evaluated as mass per unit volume, mass per unit area, or number of atoms per unit volume, the same spacer may or may not satisfy the claimed “a lower density” relationship. Claims 2-6 depend on claim 1, therefore, claims 2-6 are also indefinite. Regarding claim 3, it is not clear how the lower portion of the silicon nitride spacer is “oxygen-free”, because Applicants originally claim that the second seal layer 144 is made of silicon oxycarbide (SiOC) (Claim 1) and is in direct contact with the third seal layer 146 which is made of silicon nitride (Fig. 6 of the present application), and because the interatomic diffusion is inherent process at the interface between silicon oxycarbide and silicon nitride layers, therefore, oxygen from silicon oxycarbide would diffuse into the lower portion of the silicon nitride layer; furthermore, “the lower portion of the silicon nitride spacer” would be a bottom surface of the silicon nitride spacer, which also corresponds to a top surface of the silicon oxycarbide spacer, which inherently comprises oxygen, and therefore, it remains unclear what “the lower portion of the silicon nitride spacer” refers to, and where it is located. Regarding claim 7, it is not clear how the seal layer is “carbon-free” as recited on line 10, because Applicants originally disclosed that the second carbon-containing seal layer is directly contacted to the “carbon-free” seal layer (Fig. 6 of the present application), and therefore, interatomic diffusion of carbon is inherent process at the interface between the “carbon-free” seal layer and the second carbon-containing seal layer; furthermore, a bottom surface of the “carbon-free” seal layer would correspond to a top surface of the second carbon-containing seal layer, which inherently comprises carbon, and therefore, it is not clear what “the carbon-free seal layer” refers to, where it is located, and whether “the carbon-free seal layer” does not include the bottom surface of “the carbon-free seal layer”. Claims 8-15 depend on claim 7, therefore, claims 8-15 are also indefinite. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 7 and 14-15, as best understood, is rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Fung (US 2018/0151716). Regarding claim 1, Fung discloses a semiconductor device, comprising: a semiconductor substrate (substrate 100, Fig. 13A); a gate structure (gate stack 220, Fig. 13A) on the semiconductor substrate (100, Fig. 13A); a silicon oxycarbonitride spacer (first dielectric layer 140, Fig. 13A) on a sidewall of the gate structure (sidewall of 220, Fig. 13A), because “exemplary materials of the first dielectric layer 140 may include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon oxide, silicon nitride, silicon oxy-nitride, non-porous dielectric materials or other suitable material” (emphasis added, [0014]); a silicon oxycarbide spacer (second dielectric layer 150, Fig. 13A) on a sidewall of the silicon oxycarbonitride spacer (sidewall of 140, Fig. 13A), because “exemplary low-k dielectric material may include hydrogen doped silicon oxycarbide (SiOC:H), low-k silicon oxycarbide (SiOC), spin-on dielectric (SOD), porous silicon dioxide, porous silicon oxycarbonitride (SiOCN), low-k silicon nitride, low-k silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond ® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bisbenzocyclobutenes), SiLK (Dow Chemical of Midland, Mich.), other suitable low-k dielectric materials, and/or combinations thereof” (emphasis added, [0015]); a silicon nitride spacer (third dielectric layer 160, Fig. 13A) on a sidewall of the silicon oxycarbide spacer (sidewall of 150, Fig. 13A), because “exemplary materials of the third dielectric layer 160 may include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon oxide, silicon nitride, silicon oxy-nitride, non-porous dielectric materials or other suitable material” (emphasis added, [0017]), wherein an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer, as the claimed limitation is discussed in 35 U.S.C. 112(b) rejection above; and a source/drain structure (source/drain portion 112s, Fig. 13A) on the semiconductor substrate (100, Fig. 13A) and adjacent to the gate structure (220, Fig. 13A). Regarding claim 7, Fung further discloses for a semiconductor device, comprising: a channel pattern (channel portions 110c, Fig. 13A) over a substrate (100, Fig. 13A); a plurality of source/drain patterns (epitaxial structure 200, Fig. 13A) on opposite sides of the channel pattern (upper side of 110c, Fig. 13A); a gate pattern (gate structure 220, Fig. 13A) over the channel pattern (110c, Fig. 13A); a first carbon-containing seal layer (first dielectric layer 140, Fig. 13A) over a sidewall of the gate pattern (sidewall of 220, Fig. 13A), because “exemplary materials of the first dielectric layer 140 may include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon oxide, silicon nitride, silicon oxy-nitride, non-porous dielectric materials or other suitable material” (emphasis added, [0014]); a second carbon-containing seal layer (second dielectric layer 150, Fig. 13A) over the first carbon-containing seal layer (140, Fig. 13A), the second carbon-containing seal layer (150, Fig. 13A) being made of a different material than the first carbon-containing seal layer (140, Fig. 13A), because “exemplary low-k dielectric material may include hydrogen doped silicon oxycarbide (SiOC:H), low-k silicon oxycarbide (SiOC), spin-on dielectric (SOD), porous silicon dioxide, porous silicon oxycarbonitride (SiOCN), low-k silicon nitride, low-k silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond ® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bisbenzocyclobutenes), SiLK (Dow Chemical of Midland, Mich.), other suitable low-k dielectric materials, and/or combinations thereof” (emphasis added, [0015]), therefore, the second dielectric layer 150 by Fung can be made of different dielectric material than the first dielectric layer 140, and having a lower dielectric constant than the first carbon-containing seal layer (140, Fig. 13A), because “the second dielectric layer 150 has a dielectric constant less than that of the first dielectric layer 140” ([0015]); and a carbon-free seal layer (third dielectric layer 160, Fig. 13A) over the second carbon-containing seal layer (150, Fig. 13A), wherein the carbon-free seal layer (160, Fig. 13A) is doped with oxygen, because Fung further discloses that “exemplary materials of the third dielectric layer 160 may include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon oxide, silicon nitride, silicon oxy-nitride, non-porous dielectric materials or other suitable material” (emphasis added, [0017]), therefore, when the third dielectric layer 160 by Fung is made of silicon oxynitride (SiON), it may correspond to the silicon nitride doped with oxygen. See 35 U.S.C. 112(b) rejection above for the term “carbon-free”. Regarding claim 14, Fung further discloses for the semiconductor device of claim 7, wherein the second carbon-containing seal layer (150, Fig. 13A) is made of a porous dielectric material, because “exemplary low-k dielectric material may include hydrogen doped silicon oxycarbide (SiOC:H), low-k silicon oxycarbide (SiOC), spin-on dielectric (SOD), porous silicon dioxide, porous silicon oxycarbonitride (SiOCN), low-k silicon nitride, low-k silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond ® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bisbenzocyclobutenes), SiLK (Dow Chemical of Midland, Mich.), other suitable low-k dielectric materials, and/or combinations thereof” (emphasis added, [0015]). Regarding clam 15, Fung further discloses for the semiconductor device of claim 7, wherein the carbon-free seal layer (160, Fig. 13A) is made of a non-porous dielectric material, “exemplary materials of the third dielectric layer 160 may include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon oxide, silicon nitride, silicon oxy-nitride, non-porous dielectric materials or other suitable material” (emphasis added, [0017]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10-13, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over by Fung (US 2018/0151716). Regarding claim 10, Fung does not explicitly disclose that the carbon-free seal layer (160, Fig. 13A) has a greater dielectric constant than the second carbon-containing seal layer (150, Fig. 13A). However, Fung further discloses that “the dielectric constant of the second dielectric layer 150 may range from about 1.5 to about 3.7” ([0015]) and “the third dielectric layer 160 has a dielectric constant greater than about 3.7” ([0017]), therefore, the dielectric constant of the third dielectric layer 160 by Fung can be greater than that of the second dielectric layer 150, as claimed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multi-layers of gate spacer having different dielectric constant for each layer, as disclosed by Fung, in order to optimize electrical properties of FinFET device. Regarding claim 11, Fung further discloses that the first carbon-containing seal layer (140, Fig. 13A) has a dielectric constant in a range from about 5.5 to 6.5, because “the first dielectric layer 140 has a dielectric constant greater than about 3.7” ([0014]), therefore, the range of dielectric constant of the first dielectric layer by Fung overlaps with the claimed range. Regarding claim 12, Fung further discloses that the second carbon-containing seal layer (150, Fig. 13A) has a dielectric constant in a range from about 2.8 to 3.8, because “the dielectric constant of the second dielectric layer 150 may range from about 1.5 to about 3.7”, “the dielectric constant of the second dielectric layer 150 may range from about 2.2 to about 3.2”, and “the dielectric constant thereof may range from about 3.5 to about 3.9” ([0015]), therefore, the range of dielectric constant of the second dielectric layer by Fung overlaps with the claimed range. Regarding claim 13, Fung further discloses that the carbon-free seal layer (160, Fig. 13A) has a dielectric constant in a range from about 4.5 to 5.5, because “the third dielectric layer 160 has a dielectric constant greater than about 3.7” ([0017]), therefore, the range of dielectric constant of the third dielectric layer by Fung overlaps with the claimed range. Allowable Subject Matter Claims 16-20 are allowed, because the prior art cited in this Office Action does not teach the claimed limitation, “wherein the silicon nitride layer has an oxygen atomic percentage in a range from about 20% to 50%, and an upper portion of the silicon nitride layer has a higher oxygen atomic percentage than a lower portion of the silicon nitride layer” recited on lines 11-13 of claim 16, and claims 17-20 depend on claim 16. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /WOO K LEE/Examiner, Art Unit 2815
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Prosecution Timeline

Jul 29, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
95%
With Interview (+12.8%)
3y 2m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 204 resolved cases by this examiner. Grant probability derived from career allowance rate.

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